11 research outputs found

    Modeling, Analysis and Design of Reliable Digital Imaging System

    Get PDF
    Charge Coupled Device (CCD) is one of the most popular imaging sensors such as digital camera, digital camcorders, and digital x-ray diagnosis systems to mention a few. As the need for high resolution and high sensitive CCDs, high yield and solid reliability are becoming critical requirements for CCDs. In this context, soft-test/repair method must be developed to achieve high yield and reliability for CCDs. The purpose of this study was to propose soft-test and repair methods for defective pixels in CCD system, thereby realizing more reliable and cost-effective CCD Systems. Various test/repair algorithms are proposed and verified, and BIST/BISR architecture was proposed and the design was verified through verilog HDL simulation. Extensive parametric simulation results are also shown.Computer Science Departmen

    Modeling and Analysis of Soft-Test/Repair for CCD-Based Digital X-Ray Systems

    Get PDF
    Modern X-ray imaging systems evolve toward digitization for reduced cost, faster time-to-diagnosis, and improved diagnostic confidence. For the digital X-ray systems, charge coupled device (CCD) technology is commonly used to detect and digitize optical X-ray image. This paper presents a novel soft-test/repair approach to overcome the defective pixel problem in CCD-based digital X-ray systems through theoretical modeling and analysis of the test/repair process. There are two possible solutions to cope with the defective pixel problem in CCDs: one is the hard-repair approach and another is the proposed soft-test/repair approach. Hard-repair approach employs a high-yield, expensive reparable CCD to minimize the impact of hard defects on the CCD, which occur in the form of noise propagated through A/D converter to the frame memory. Therefore, less work is needed to filter and correct the image at the end-user level while it maybe exceedingly expensive to practice. On the other hand, the proposed soft-test/repair approach is to detect and tolerate defective pixels at the digitized image level; thereby, it is inexpensive to practice and on-line repair can be done for noninterrupted service. It tests the images to detect the detective pixels and filter noise at the frame memory level and caches them in a flash memory in the controller for future repair. The controller cache keeps accumulating all the noise coordinates and preprocesses the incoming image data from the A/D converter by repairing them. The proposed soft-test/repair approach is particularly devised to facilitate hardware level implementation ultimately for real-time telediagnosis. Parametric simulation results demonstrate the speed and virtual yield enhancement by using the proposed approach; thereby highly reliable, yet inexpensive, soft-test/repair of CCD-based digital X-ray systems can be ultimately realized

    pH-responsive high-density lipoprotein-like nanoparticles to release paclitaxel at acidic pH in cancer chemotherapy

    Get PDF
    Jae-Yoon Shin,1,* Yoosoo Yang,1,* Paul Heo,1 Ji-Chun Lee,1 ByoungJae Kong,1 Jae Youl Cho,1 Keejung Yoon,1 Cheol-Su Shin,2 Jin-Ho Seo,3 Sung-Gun Kim,4 Dae-Hyuk Kweon11Department of Genetic Engineering, College of Biotechnology and Bioengineering, and Center for Human Interface Nano Technology, Sungkyunkwan University, 2APTech Research Center, Suwon, 3Department of Agricultural Biotechnology, Seoul National University, Seoul, 4Department of Biomedical Science, Youngdong University, Chungbuk, South Korea*These authors contributed equally to this workBackground: Nanoparticles undergoing physicochemical changes to release enclosed drugs at acidic pH conditions are promising vehicles for antitumor drug delivery. Among the various drug carriers, high-density lipoprotein (HDL)-like nanoparticles have been shown to be beneficial for cancer chemotherapy, but have not yet been designed to be pH-responsive.Methods and results: In this study, we developed a pH-responsive HDL-like nanoparticle that selectively releases paclitaxel, a model antitumor drug, at acidic pH. While the well known HDL-like nanoparticle containing phospholipids, phosphatidylcholine, and apolipoprotein A-I, as well as paclitaxel (PTX-PL-NP) was structurally robust at a wide range of pH values (3.8–10.0), the paclitaxel nanoparticle that only contained paclitaxel and apoA-I selectively released paclitaxel into the medium at low pH. The paclitaxel nanoparticle was stable at physiological and basic pH values, and over a wide range of temperatures, which is a required feature for efficient cancer chemotherapy. The homogeneous assembly enabled high paclitaxel loading per nanoparticle, which was 62.2% (w/w). The molar ratio of apolipoprotein A-I and paclitaxel was 1:55, suggesting that a single nanoparticle contained approximately 110 paclitaxel particles in a spherical structure with a 9.2 nm diameter. Among the several reconstitution methods applied, simple dilution following sonication enhanced the reconstitution yield of soluble paclitaxel nanoparticles, which was 0.66. As a result of the pH responsiveness, the anticancer effect of paclitaxel nanoparticles was much more potent than free paclitaxel or PTX-PL-NP.Conclusion: The anticancer efficacy of both paclitaxel nanoparticles and PTX-PL-NP was dependent on the expression of scavenger receptor class B type I, while the killing efficacy of free paclitaxel was independent of this receptor. We speculate that the pH responsiveness of paclitaxel nanoparticles enabled efficient endosomal escape of paclitaxel before lysosomal break down. This is the first report on pH-responsive nanoparticles that do not contain any synthetic polymer.Keywords: pH responsiveness, nanoparticle, apolipoprotein A-I, paclitaxe

    iv TABLE OF CONTENTS

    No full text
    I would like to acknowledge many people for helping me during my doctoral work. I would especially like to thank my advisor, Dr. Nohpill Park, for his generous time and commitment. Throughout my doctoral work he encouraged me to develop independent thinking and research skills. He continually stimulated my analytical thinking and greatly assisted me with scientific writing. I am also very grateful for having an exceptional doctoral committee and wish to thank Dr. K.M. George, Dr. V. Sarangan and Dr. G. Fan for their continual support and encouragement. Finally, I’d like to thank my family. My father gave me his true love and endless trust. I hope he could live to see his grandson’s college admission ceremony. My mother was a constant source of support. I thank my sisters for their encouragement and enthusiasm. I would like to give my special thanks to parents-in-law and sistersin-law. I’m especially grateful to my wife Bongran and my beloved son Luke(2) fo

    Designing Layout-Timing Independent Quantum-Dot Cellular Automata (QCA) Circuits by Global Asynchrony

    No full text
    The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the layout = timing problem. to circumvent the problem, a novel self-timed QCA circuit design methodology referred to as the Globally Asynchronous, Locally Synchronous (GALS) Design for QCA is proposed in this paper. the proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design and floorplanning will be possible

    Regressive Testing for System-on-Chip with Unknown-Good-Yield

    No full text
    This paper presents a testing method for electronic devices with no a-priori yield information. This problem is referred to as Unknown-Good-Yield (UKGY) problem. The UKGY problem of Systems-on-Chip (SoC) is discussed in this paper as SoCs are in general built with embedded Intellectual Property (IP) Cores, each of which procured from IP providers with no information on Known-Good-Yield (KGY). In general, partial testing is a practical choice for assuring the yield of the product under the stringent time-to-market requirement in today\u27s high density/complexity electronic devices such as SoC built with deep submicron or nano technology. Therefore, efficient and effective sampling technique is a key to the success of high confidence testing. An Experimental Characterization-based Testing (referred to as ET) method for SoC has been proposed prior to this work, in which a stratified sampling method was employed based on environmental-based characterization and experimental design technique to enhance the confidence level of the estimation of yield. The proposed testing method, referred to as Regressive Testing (RegT), in this paper exploits another way around by using parameters (referred to as Assistant Variables (AV) free from UKGY that determines the criteria to sample and test SoCs, and employs the regression analysis method to evaluate the yield with regard to confidence interval. A numerical simulation is conducted to demonstrate the efficiency and effectiveness of the proposed RegT in comparison with generic random testing method

    Soft-Test/Repair of CCD-Based Digital X-Ray Instrumentation

    No full text
    Modern x-ray imaging systems evolve toward digitization for reduced cost, faster time-to-diagnosis and improved diagnostic confidence. For the digital x-ray systems, CCD (Charge Coupled Device) technology is commonly used to detect and digitize optical x-ray image. This paper presents a novel soft-test/repair approach to overcome the defective pixel problem in CCD (Charge Coupled Device)-based digital x-ray system through theoretical modeling and analysis of the test/repair process. There are two possible solutions to cope with the defective pixel problem in CCD; one is the hard-repair approach and another is the proposed soft-test/repair approach. Hard-repair approach employs a high-yield, expensive reparable CCD to minimize the impact of hard-defects on the CCD, which occur in the form of noise propagated through AID converter to the frame memory, Therefore, less work is needed to filter and correct the image at the end-user level while it maybe exceedingly expensive to practice. On the other hand, the proposed soft-test/repair approach is to detect and tolerate defective pixels at the digitized image level; thereby it is inexpensive to practice and on-line repair can be done for non-interrupted service. It tests the images to detect the detective pixels and filter noise at the frame memory level, and caches them in a flash memory in the controller for future repair. The controller cache keeps accumulating all the noise coordinates, and preprocesses the incoming image data from the A/D converter by repairing them. The proposed soft-test/repair approach is particularly devised to facilitate hardware level implementation ultimately for real-time tele-diagnosis. Parametric simulation results demonstrate the speed and virtual yield enhancement by using the proposed approach; thereby highly reliable, yet inexpensive soft-test/repair of CCD-based digital x-ray systems can be ultimately realized

    Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems

    No full text
    A highly dependable embedded fault-tolerant memory architecture for high performance massively parallel computing applications and its dependability assurance techniques are proposed and discussed in this paper. The proposed fault tolerant memory provides two distinctive repair mechanisms: the permanent laser redundancy reconfiguration during the wafer probe stage in the factory to enhance its manufacturing yield and the dynamic BIST/BISD/BISR (built-in-self-test-diagnosis-repair)-based reconfiguration of the redundant resources in field to maintain high field reliability. The system reliability which is mainly determined by hardware configuration demanded by software and field reconfiguration/repair utilizing unused processor and memory modules is referred to as HW/SW Co-reliability. Various system configuration options in terms of parallel processing unit size and processor/memory intensity are also introduced and their HW/SW Co-reliability characteristics are discussed. A modeling and assurance technique for HW/SW Co-reliability with emphasis on the dependability assurance techniques based on combinatorial modeling suitable for the proposed memory design is developed and validated by extensive parametric simulations. Thereby, design and Implementation of memory-reliability-optimized and highly reliable fault-tolerant field reconfigurable massively parallel computing systems can be achieved
    corecore