High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems

The technological development is enabling production of increasingly complex electronic systems. All those systems must be verified and tested to guarantee correct behavior. As the complexity grows, testing is becoming one of the most significant factors that contribute to the final product cost. The established low-level methods for hardware testing are not any more sufficient and more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. This thesis reports on one such work that deals in particular with high-level test generation and design for testability techniques. The contribution of this thesis is twofold. First, we investigate the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation architecture. We have developed for this purpose a novel hierarchical test generation algorithm and demonstrated the usefulness of the generated tests not only for manufacturing test but also for testability analysis. The second part of the thesis concentrates on design for testability. As testing of modern complex electronic systems is a very expensive procedure, special structures for simplifying this process can be inserted into the system during the design phase. We have proposed for this purpose a novel hybrid built-in self-test architecture, which makes use of both pseudorandom and deterministic test patterns, and is appropriate for modern system-on-chip designs. We have also developed methods for optimizing hybrid built-in self-test solutions and demonstrated the feasibility and efficiency of the proposed technique.Report code: LiU-Tek-Lic-2002:46.</p

Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems

The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques. In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST. Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation. Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques

System-level communication synthesis and dependability improvements for Network-on-Chip based systems

Abstract. Technology scaling into subnanometer range will create process variations that have impact on the overall manufacturing yield and quality. Smaller feature sizes permit to pack more functionality into a single chip. Increasing variability, complexity and communication bandwidth requirements will make the System-on-Chip designer’s goal, to design a fault-free system, a very difficult task. Shift from traditional bus-based systems to networked systems solves several design problems but requires more focus on communication modelling. In this work we propose a systemlevel approach for communication modelling and synthesis. It makes possible to calculate precise communication delays that can be taken into account during application scheduling to avoid network congestions. We present a possible application of the proposed framework for scheduling fault-tolerant applications on non-reliable network. Key words: communication synthesis, Network-on-Chip, dependability, system-level design. 1

Test Time Minimization for Hybrid BIST of Core-Based Systems

Abstract 1 This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find a near optimal solutions. 1

A Hybrid BIST Architecture and its Optimization for SoC Testing

This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without losing test quality. We propose two algorithms to calculate the cost of the test process. To speed up the optimization procedure, a Tabu search based method is employed for finding the global cost minimum. Experimental results have demonstrated the feasibility and efficiency of the approach and the significant decreases in overall test cost

A Hierarchical Test Generation Technique for Embedded Systems

1 This paper presents a hierarchical test generation technique for embedded systems containing hardware and software. The technique is applied to the system-level specification of such systems. Different from the traditional approaches, hardware and software parts of an embedded system are handled in a uniform way. We will in particular show how the proposed technique can be applied at high levels of abstraction and how the software domain of the specification can also be successfully covered. 1. Introduction The development of hardware/software codesign techniques has made it possible to design hardware and software of an embedded system at the high levels of abstraction in a uniform way. However the testing of the hardware and software parts of the system are still considered as totally unrelated problems and solved with very different methods. In the early phases of the design cycle, system synthesis is performed starting from an implementation independent specification. Reasonin..