Vampires in the village Žrnovo on the island of Korčula: following an archival document from the 18th century

Središnja tema rada usmjerena je na raščlambu spisa pohranjenog u Državnom arhivu u Mlecima (fond: Capi del Consiglio de’ Dieci: Lettere di Rettori e di altre cariche) koji se odnosi na događaj iz 1748. godine u korčulanskom selu Žrnovo, kada su mještani – vjerujući da su se pojavili vampiri – oskvrnuli nekoliko mjesnih grobova. U radu se podrobno iznose osnovni podaci iz spisa te rečeni događaj analizira u širem društvenom kontekstu i prate se lokalna vjerovanja.The main interest of this essay is the analysis of the document from the State Archive in Venice (file: Capi del Consiglio de’ Dieci: Lettere di Rettori e di altre cariche) which is connected with the episode from 1748 when the inhabitants of the village Žrnove on the island of Korčula in Croatia opened tombs on the local cemetery in the fear of the vampires treating. This essay try to show some social circumstances connected with this event as well as a local vernacular tradition concerning superstitions

Characterization of chemical vapor deposited polycrystalline silicon thin films

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1986.MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERINGBibliography: leaves 134-139.by Jean-Jacques Joseph Hajjar.M.S

Prediction Of Gate Dielectric Breakdown In The Cdm Timescale Utilizing Very Fast Transmission Line Pulsing

In this paper, prediction of Gate Oxide Breakdown (GOB) in the Charged Device Model (CDM) timeframe is performed. The prediction does not require lengthy low-voltage Constant Voltage Stress (CVS) measurements but instead utilizes short (less than 5 seconds per measurement) high-voltage CVS measurements as well as quick Ramped Voltage Stress (RVS) measurements to calculate a voltage to breakdown (VBD) in the CDM timeframe as well as the dispersal of actual TDDBs for each oxide area and thickness. To this end, a modified form of the Power Law, called the Trapezoidal Power Law, is derived to simplify data processing and allow comparisons between RVS and CVS. The prediction methodology using the Trapezoidal Power Law is finally demonstrated to predict the exact voltage required to consistently damage the oxide within a single pulse. ©2009 IEEE

Analysis Of Safe Operating Area Of Nldmos And Pldmos Transistors Subject To Transient Stresses

Transient safe operating area (TSOA) of n-type and p-type laterally diffused metaloxidesemiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA. © 2006 IEEE

Bidirectional Devices For Automotive-Grade Electrostatic Discharge Applications

Color sequential projection display using a vertical field switching (VFS) polymer-stabilized blue phase liquid crystal (BPLC) is proposed. The VFS-BPLC exhibits submillisecond response time which is useful for suppressing color breakup. The proposed projector also has a small throw ratio. With phase compensation, the distortion from oblique LC panel could be corrected. © 2012 IEEE

Nldmos Esd Scaling Under Human Metal Model For 40-V Mixed-Signal Applications

Electrostatic discharge (ESD) robustness of LDMOS (laterally diffused MOS) devices is found to be highly dependent on the type of ESD stress. In particular, the device\u27s ESD robustness does not scale with the device width, and this condition is substantially aggravated during the International Electrotechnical Commission (IEC) 61000-4-2 stress condition. IEC 61000-4-2 is a system-level ESD standard increasingly being adopted in the industry for ESD robustness assessment at the integrated circuit level. A comprehensive evaluation under the IEC 61000-4-2 stress impacting precision circuit designs is introduced in this letter for variable width LDMOS devices fabricated in a 0.18-μm bipolar-CMOS-DMOS process for 40-V mixed-signal applications. © 2012 IEEE

Prediction of Gate Dielectric Breakdown in the CDM timescale utilizing very fast transmission line pulsing

In this paper, prediction of Gate Oxide Breakdown (GOB) in the Charged Device Model (CDM) timeframe is performed. The prediction does not require lengthy low-voltage Constant Voltage Stress (CVS) measurements but instead utilizes short (less than 5 seconds per measurement) high-voltage CVS measurements as well as quick Ramped Voltage Stress (RVS) measurements to calculate a voltage to breakdown (VBD) in the CDM timeframe as well as the dispersal of actual TDDBs for each oxide area and thickness. To this end, a modified form of the Power Law, called the Trapezoidal Power Law, is derived to simplify data processing and allow comparisons between RVS and CVS. The prediction methodology using the Trapezoidal Power Law is finally demonstrated to predict the exact voltage required to consistently damage the oxide within a single pulse. ©2009 IEEE