IMPLEMENTATION OF MOTION ESTIMATION BASED ON HETEROGENEOUS PARALLEL COMPUTING SYSTEM WITH OPENC

International audienceHeterogeneous computing system increases the performance of parallel computing in many domain of general purpose computing with CPU, GPU and other accelerators. Open Computing Language (OpenCL) is the first open, royaltyfree standard for heterogenous computing on multi hardware platforms. In this paper, we propose a parallel Motion Estimation (ME) algorithm implemented using OpenCL and present several optimization strategies applied in our OpenCL implementation of the motion estimation. In the same time, we implement the proposed algorithm on our heterogeneous computing system which contains one CPU and one GPU, and propose one method to determine the balance to distribute the workload in heterogeneous computing system with OpenCL. According to experiments, our motion estimator with achieves 100 to 150 speed-up compared with its implementation with C code executed by single CPU core and our proposed method obtains obviously enhancement of performance in based on our heterogeneous computing system

Full Stock Payment Marginalization in M&A Transactions

The number of merger and acquisition (M&A) transactions paid fully in stock in the U.S. market declined sharply after 2001, when pooling and goodwill amortization were abolished by the Financial Accounting Standards Board. Did this accounting rule change really have such far-reaching implications? Using a differences-in-differences test and Canada as a counterfactual, this study reveals that it did. We also report several other results confirming the role of pooling abolishment, including (i) that the decrease in full stock payment relates to CEO incentives and (ii) that previously documented determinants of the M&A mode of payment cannot explain the post pooling abolishment pattern. These results are also robust to controls for various factors, such as the Internet bubble, the exclusion of cross-border deals, the presence of Canadian cross-listed firms, the use of a constant sample of acquirers across the pooling and post pooling abolishment periods, the use of Europe as an alternative counterfactual, and controls for the SEC Rule 10b-18 share repurchase safe harbor amendments of 2003

A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention

International audienceTask scheduling is an important aspect for parallel programming. In this paper, the program to be scheduled is modeled as a Directed Acyclic Graph (DAG), and we target parallel embedded systems of multiple processors connected by buses and switches. This paper presents improvements for list scheduling heuristics with communication contention. We use new node priorities (top level and bottom level) to sort nodes and use an advanced technique of critical child to select a processor to execute a node. Experimental results show that our method is effective to reduce the schedule length, and the performance is greatly improved in the cases of medium and high communication. Since the communication cost is increasing from medium to high in modern applications like digital communication and video compression, our method will work well for scheduling these applications on parallel embedded systems

Advanced list scheduling heuristic for task scheduling with communication contention for parallel embedded systems

WOSInternational audienceModern embedded systems tend to use multiple cores or processors for processing parallel applications. This paper indeed aims at task scheduling with communication contention for parallel embedded systems and proposes three advanced techniques to improve the list scheduling heuristic. Five groups of node levels (two existing groups and three new groups) are firstly used as node priorities to generate node lists. Then the critical child technique improves the selection of a processor in the scheduling process. Finally, the communication delay technique enlarges the idle time intervals on communication links. We also propose an advanced dynamic list scheduling heuristic by combining the three techniques. Experimental results show that the combined advanced dynamic heuristic is efficient to shorten the schedule length for most of the randomly generated DAGs in the cases of medium and high communication. Our method accelerates an application up to 80% in the case of high communication and can also reduce the use of hardware resources

Heuristique statique améliorée d'ordonnancement de tâches: impact sur le tri des tâches et sur l'allocation de processeur

National audienceL'ordonnancement de tâches est une étape importante dans le prototypage rapide d'applications de traitement d'images sur des systèmes parallèles embarqués. Nous présentons ainsi dans cet article une heuristique statique améliorée d'ordonnancement par liste : d'une part, cette heuristique intègre de nouvelles règles de priorité de tâches, tenant compte de la contention sur les communications entre tâches ; d'autre part, cette heuristique affine l'allocation d'un processeur à une tâche courante, en impactant le choix du processeur par un ordonnancement partiel de la tâche successeur critique (" critical child ") à la tâche courante. Nos résultats expérimentaux soulignent une accélération effective de l'application implantée, dans un contexte de moyenne comme de forte communication

A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention

International audienceTask scheduling is an important aspect for parallel programming. In this paper, the program to be scheduled is modeled as a Directed Acyclic Graph (DAG), and we target parallel embedded systems of multiple processors connected by buses and switches. This paper presents improvements for list scheduling heuristics with communication contention. We use new node priorities (top level and bottom level) to sort nodes and use an advanced technique of critical child to select a processor to execute a node. Experimental results show that our method is effective to reduce the schedule length, and the performance is greatly improved in the cases of medium and high communication. Since the communication cost is increasing from medium to high in modern applications like digital communication and video compression, our method will work well for scheduling these applications on parallel embedded systems

Empirical Evidence of Overbidding in M&A Contests

Surprisingly few papers have attempted to develop a direct empirical test for overbidding in M&A contests. We develop such a test grounded on a necessary condition for profit maximizing bidding behavior. The test is not subject to endogeneity concerns. Our results strongly support the existence of overbidding. We provide evidence that overbidding is related to conflicts of interest, but also some indirect evidence that it arises from failing to fully account for the winner’s curse

Improved Methods for Detecting Acquirer Skills

Large merger and acquisition (M&A) samples feature the pervasive presence of repetitive acquirers. They offer an attractive empirical context for revealing the presence of acquirer skills (persistent superior performance). But panel data M&A are quite heterogeneous; just a few acquirers undertake many M&As. Does this feature affect statistical inference? To investigate the issue, our study relies on simulations based on real data sets. The results suggest the existence of a bias, such that extant statistical support for the presence of acquirer skills appears compromised. We introduce a new resampling method to detect acquirer skills with attractive statistical properties (size and power) for samples of acquirers that complete at least five acquisitions. The proposed method confirms the presence of acquirer skills but only for a marginal fraction of the acquirer population. This result is robust to endogenous attrition and varying time periods between successive transactions. Claims according to which acquirer skills are a first order factor explaining acquirer cross-­‐sectional cumulated abnormal returns appears overstated

Heuristique statique améliorée d'ordonnancement de tâches: impact sur le tri des tâches et sur l'allocation de processeur

National audienceL'ordonnancement de tâches est une étape importante dans le prototypage rapide d'applications de traitement d'images sur des systèmes parallèles embarqués. Nous présentons ainsi dans cet article une heuristique statique améliorée d'ordonnancement par liste : d'une part, cette heuristique intègre de nouvelles règles de priorité de tâches, tenant compte de la contention sur les communications entre tâches ; d'autre part, cette heuristique affine l'allocation d'un processeur à une tâche courante, en impactant le choix du processeur par un ordonnancement partiel de la tâche successeur critique (" critical child ") à la tâche courante. Nos résultats expérimentaux soulignent une accélération effective de l'application implantée, dans un contexte de moyenne comme de forte communication

Implementation of Stereo Matching Using High Level Compiler for Parallel Computing Acceleration

International audienceHeterogeneous computing system increases the performance of parallel computing in many domain of general purpose computing with CPU, GPU and other accelerators. With Hardware developments, the software developments like Compute Unified Device Architecture(CUDA) and Open Computing Language (OpenCL) try to offer a simple and visualized tool for parallel computing. But it turn out to be more difficult than programming on CPU platform for optimization of performance. For one kind of parallel computing application, there are different configuration and parameters for various hardware platforms. In this paper, we apply the Hybrid Multi-cores Parallel Programming(HMPP) to automatic-generates tunable code for GPU platform and show the result of implementation of Stereo Matching with detailed comparison with C code version and manual CUDA version. The experimental results show that the default and optimized HMPP have the approximative 1 compared with CUDA implementation. And the HMPP workbench can greatly reduce the time of application development using parallel computing device