A flexible heterogeneous video processor system for television applications

A new video processing architecture for high-end TV applications is presented, featuring a flexible heterogeneous multi-processor architecture, executing video tasks in parallel and independently. The signal flow graph and the processors are programmable, enabling an optimal picture quality for different TV display modes. The concept is verified by an experimental chip design. The architecture allows several video streams to be processed and displayed in parallel and in a programmable way, with an individual signal qualit

Phylogenetic organization of bacterial activity.

Phylogeny is an ecologically meaningful way to classify plants and animals, as closely related taxa frequently have similar ecological characteristics, functional traits and effects on ecosystem processes. For bacteria, however, phylogeny has been argued to be an unreliable indicator of an organism\u27s ecology owing to evolutionary processes more common to microbes such as gene loss and lateral gene transfer, as well as convergent evolution. Here we use advanced stable isotope probing with (13)C and (18)O to show that evolutionary history has ecological significance for in situ bacterial activity. Phylogenetic organization in the activity of bacteria sets the stage for characterizing the functional attributes of bacterial taxonomic groups. Connecting identity with function in this way will allow scientists to begin building a mechanistic understanding of how bacterial community composition regulates critical ecosystem functions.The ISME Journal advance online publication, 4 March 2016; doi:10.1038/ismej.2016.28

Compression for reduction of off-chip video bandwidth

The architecture for block-based video applications (e.g. MPEG/JPEG coding, graphics rendering) is usually based on a processor engine, connected to an external background SDRAM memory where reference images and data are stored. In this paper, we reduce the required memory bandwidth for MPEG coding up to 67% by identifying the optimal block configuration and applying embedded data compression up to a factor four. It is shown that independent compression of fixed-sized data blocks with a fixed compression ratio can decrease the memory bandwidth for a limited set of compression factors only. To achieve this result, we exploit the statistical properties of the burst-oriented data exchange to memory. It has been found that embedded compression is particularly attractive for bandwidth reduction when a compression ratio 2 or 4 is chosen. This moderate compression factor can be obtained with a low-cost compression scheme such as DPCM with a small acceptable loss of quality

Bandwidth reduction for video processing in consumer systems

The architecture of the present video processing units in consumer systems is usually based on various forms of processor hardware, communicating with an off-chip SDRAM memory. Examples of these systems are currently available MPEG encoders and decoders, and high-end television systems. Due to the fast increase of required computational power of consumer systems, the data communication to and from the off-chip memory has become the bottleneck in the overall system performance (memory wall problem). This paper presents a strategy for mapping pixels into the memory for video applications such as MPEG processing, thereby minimizing the transfer overhead between memory and the processing. A novelty in our approach is that the proposed communication model considers the statistics of the application-dependent data accesses in memory. With this technique, a 26% reduction of the memory bandwidth was obtained in an MPEG decoding system containing a 64-bit wide memory bus. For double-data-rate SDRAM (DDR SDRAM), the proposed mapping strategy reduces the bandwidth in the system by even 50%. This substantial performance improvement can readily be used for extending the quality or the functionality of the syste

Bandwidth reduction for video processing in consumer systems

The architecture of the present video processing units in consumer systems is usually based on various forms of processor hardware, communicating with an off-chip SDRAM memory. Examples of these systems are currently available MPEG encoders and decoders, and high-end television systems. Due to the fast increase of required computational power of consumer systems, the data communication to and from the off-chip memory has become the bottleneck in the overall system performance (memory wall problem). This paper presents a strategy for mapping pixels into the memory for video applications such as MPEG processing, thereby minimizing the transfer overhead between memory and the processing. A novelty in our approach is that the proposed communication model considers the statistics of the application-dependent data accesses in memory. With this technique, a 26% reduction of the memory bandwidth was obtained in an MPEG decoding system containing a 64-bit wide memory bus. For double-data-rate SDRAM (DDR SDRAM), the proposed mapping strategy reduces the bandwidth in the system by even 50%. This substantial performance improvement can readily be used for extending the quality or the functionality of the syste

Bandwidth Reduction for Video Processing in Consumer Systems

This paper presents a strategy for substantially improving the memory (SDRAM) bandwidth in MPEG-type videoprocessing consumer systems. A new pixel-mapping strategy is proposed that halved the memory bandwidth for MPEG decoding using a sophisticated memory device (for example DDR SDRAM)

On the design of multimedia software and future system architectures

A principal challenge for reducing the cost for designing complex systems-on-chip is to pursue more generic systems for a broad range of products. For this purpose, we explore three new architectural concepts for state-of-art video applications. First, we discuss a reusable scalable hardware architecture employing a hierarchical communication network fitting with the natural hierarchy of the application. In a case study, we show that MPEG streaming in DTV occurs at high level, while subsystems communicate at lower levels. The second concept is a software design that scales over a number of processors to enable reuse over a range of VLSI process technologies. We explore this via an H.264 decoder implementation scaling nearly linearly over up to eight processors by applying data partitioning. The third topic is resource-scalability, which is required to satisfy realtime constraints in a system with a high amount of shared resources. An example complexity-scalable MPEG-2 coder scales the required cycle budget with a factor of three, in parallel with a smooth degradation of quality