Effects of Parasitics and Interface Traps On Ballistic Nanowire FET In The Ultimate Quantum Capacitance Limit

In this paper, we focus on the performance of a nanowire Field Effect Transistor (FET) in the Ultimate Quantum Capacitance Limit (UQCL) (where only one subband is occupied) in the presence of interface traps ($D_{it}$), parasitic capacitance ($C_L$) and source/drain series resistance ($R_{s,d}$) using a ballistic transport model and compare the performance with its Classical Capacitance Limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely, (i) gate voltage dependent capacitance, (ii) saturation of the drain current, (iii) the subthreshold slope and (iv) the scaling performance. To gain physical insights into these effects, we also develop a set of semi-analytical equations. The key observations are: (1) A strongly energy-quantized nanowire shows non-monotonic multiple peak C-V characteristics due to discrete contributions from individual subbands; (2) The ballistic drain current saturates better in the UQCL compared to CCL, both in presence and absence of $D_{it}$ and $R_{s,d}$; (3) The subthreshold slope does not suffer any relative degradation in the UQCL compared to CCL, even with $D_{it}$ and $R_{s,d}$; (4) UQCL scaling outperforms CCL in the ideal condition; (5) UQCL scaling is more immune to $R_{s,d}$, but presence of $D_{it}$ and $C_L$ significantly degrades scaling advantages in the UQCL.Comment: Accepted at IEEE Transactions on Electron Device

HFinFET: A Scalable, High Performance, Low Leakage Hybrid N-Channel FET

In this letter we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of a HEMT and a FinFET, to obtain excellent performance and good off state control. Followed by the description of the design, 3D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and non-planar Si NMOSFET data of comparable gate length using standard benchmarking techniques.Comment: 3 pages, 4 figure

Intrinsic Reliability improvement in Biaxially Strained SiGe p-MOSFETs

In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility ({\mu}h) in the transport direction and alleviates charge flow towards the gate oxide. {\mu}h enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height ({\phi}) in SiGe. Similar field acceleration factor ({\Gamma}) for threshold voltage shift ({\Delta}VT) and increase in noise ({\Delta}SVG) in Si and SiGe suggests identical degradation mechanisms.Comment: 4 figures, 3 pages, accepted for publication in IEEE ED

Improved Ge surface passivation with ultrathin SiO/sub x/ enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiOX passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm2 • V−1 • s−1 at 0.05 MV/cm—a 2× enhancement over the universal Si/SiO2 mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an ION/IOFF ratio of 3 × 103 without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface

Improved Ge surface passivation with ultrathin SiO/sub x/ enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiOX passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm2 • V−1 • s−1 at 0.05 MV/cm—a 2× enhancement over the universal Si/SiO2 mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an ION/IOFF ratio of 3 × 103 without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface