Multiband LTE power amplifier for handset application / Jagadheswaran Rajendran

As wireless communication standard continues to evolve accommodating the demand of high data rate operation, the design of RF power amplifier (PA) becomes ever challenging. PAs are required to operate more efficiently while maintaining stringent linearity requirement. In this work, a new circuit to extend the linear operation bandwidth of a LTE (Long Term Evolution) power amplifier, while delivering a high efficiency is presented. The 950μm x 900μm monolithic microwave integrated circuit (MMIC) power amplifier (PA) is fabricated in a 2μm InGaP/GaAs process. The PA consists of three stages, which is the pre-driver, driver and main stages. The main stage is designed in class-J configuration in order to improve the efficiency of the PA. The optimum conduction angle method is employed to enable the PA to operate in bias condition which has the optimum operation for linearity and efficiency. A novel on-chip analog pre-distorter (APD) is designed and integrated into the driver stage to improve the linearity of the highly efficient PA further to meet the adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) specifications for LTE signal profile with 20MHz channel bandwidth. Experimental result verifies that the designed PA is capable to meet the ACLR specifications of -30dBc from 1.7GHz to 2.05GHz which encapsulates LTE Band 1,2,3,4,9,10,33,34,35,36,37 and 39 at maximum linear output power of 28dBm. The maximum EVM at 28dBm for 16-QAM scheme is 3.38% at 2050MHz.The corresponding power added efficiency (PAE) varies from 40.5% to 55.8% across band. With a respective input return loss of less than -15dB, the PA’s maximum power gain is measured to be 35.8dB while exhibiting an unconditional stability characteristic from DC up to 5GHz. The proposed architecture serves to be a good solution to improve the linearity and efficiency of a PA for wideband LTE operation without sacrificing other critical performance metrics. This will ultimately reach the goal to have single chip solution for handset LTE PA

A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving – 120 dBc/Hz Phase Noise at 1 MHz Offset

The performance of low-powered transceivers is required to meet stringent specifications for an advanced wireless radio application. It is critical for a voltage-controlled oscillator (VCO) to meet multi-standard and multiple frequency operation with low-power consumption and amplitude enhanced complementary mode of operation. This paper proposes a novel technique for wide tuning range in a complementary class-C VCO employing a capacitive-source degeneration (CSD) to meet multi-standard operation for low-power transceivers. The technique that employs two sets of symmetrical split PMOS biased current source operating in the subthreshold region achieves the desired low phase noise (PN) performance at a tuning range of 2.2-2.9 GHz with a supply headroom of 1.2 V. The control of the dc bias point reduces the conduction angle, which improves the current efficiency, power consumption, and PN. Concurrently, an auxiliary $-g_{m}$ NMOS only class-B oscillator is incorporated to mitigate the start-up issue of the class-C VCO. At the center frequency of 2.45 GHz, the proposed VCO achieves a power consumption of 1.73 mW, phase noise of-120 dBc/Hz at the 1-MHz offset, and a figure-of-merit (FoM) of 185.41 dBc/Hz at 1 MHz. The total active chip area is only 0.3-mm2 excluding bond pads. The proposed VCO serves as a promising solution for low-power wireless communication systems. © 2013 IEEE

Parallel-pipelined-memory Blowfish FPGA-based radio system with improved power-throughput for secured IoT network

The Internet of Things (IoT) has emerged as a disruptive force, transforming industries, cities, and daily life in a time of unprecedented connection. This outcome has called for robust security, reliability, and efficient power management for the IoT network. The security of small mobile devices within the IoT network has become a pressing concern due to the multitude of wireless vulnerabilities that threaten data transmission, the harsh wireless environment for data transmission, and the need for low-power consumption devices. This study proposed the development of a new parallel-pipelined-memory (P2M) Blowfish field programmable gate array (FPGA)-based radio system as a prototype of a secured mobile device for IoT application. The FPGA platform verified the proposed system, indicating a minimum of 64 % power-throughput improvement. In this case, the hardware utilisation was reduced by 3.5 % compared to the recently published works. Meanwhile, the real-time transmission analysis of the suggested P2M Blowfish radio system in a non-line-of-sight (NLOS) indoor environment indicated that the transmitted data over 2.4 GHz ZigBee standard at 10 dBm radio frequency (RF) power level demonstrated the optimum signal quality with received signal strength and signal-to-noise ratio (SNR) of −34.58 dBm and 39.06 dB, respectively. This feature also included a 6.25 × 10−3 minimum bit error rate (BER) at 61 m as the maximum communication range. Thus, the P2M Blowfish FPGA-based radio system could improve the security, reliability, and power efficiency of IoT networks

A high gain 10 watts wideband distributed power amplifier for two way radio system

Purpose – This paper aims to propose a practical design methodology of high-power wideband power amplifier. Design/methodology/approach – The distributed power amplification method is used for a Gallium Nitride device to achieve wideband operation. To achieve the high power without trading-off the bandwidth and gain, a methodology to extract the package-loading effect is proposed and verified. Findings – A maximum output power of 10 W is achieved from 100 MHz to 2 GHz with a wideband power gain of 32 dB in measurement. This performance is achieved through a single section matching network. Research limitations/implications – Measurement accuracy is dependable to the thermal behaviour of the high-power device. Practical implications – The proposed technique is an excellent solution to be used in the two way radio power amplifier that minimizes the fundamental trade-off issue between power, gain, bandwidth and efficiency. Originality/value – In this work, a practical distributed power amplifier (DPA) design methodology is proposed that reduces the development cycle time for industrial engineers working on high-power circuit design application

A 0.8 mm(2) Sub-GHz GaAs HBT Power Amplifier for 5G Application Achieving 57.5% PAE and 28.5 dBm Maximum Linear Output Power

This paper presents a comprehensive design of a fully integrated multistage GaAs HBT power amplifier that achieves both linearity and high efficiency within a chip area of 0.855 mm(2) for 4G and 5G applications covering the lower frequency band of 700-800 MHz. A novel linearizer circuit is integrated to a dual stage class-AB PA to minimize the AM-PM (Amplitude Modulation-Phase Modulation) distortion generated by the parasitic capacitance at the PN-junction under low bias current condition. The linearized power amplifier is able to operate within a 100 MHz linear operating bandwidth (700-800 MHz) while meeting the adjacent channel leakage ratio (ACLR) specification for 4G and 5G application. The fully integrated PA achieves a wideband efficiency of 57.5% at 28.5 dBm output power. Observing a respective input and output return losses of less than 13 dB and 10 dB, the PA delivers a power gain within the range of 34.0-37.0 dB across the operating bandwidth while exhibiting an unconditional stability characteristic from DC up to 5 GHz. The proposed linearization method paves the way of reducing the complexity of linear and high efficiency PA design which is associated with complicated and high-power consumption linearization schemes

A 0.8 mm2 Sub-GHz GaAs HBT Power Amplifier for 5G Application Achieving 57.5% PAE and 28.5 dBm Maximum Linear Output Power

This paper presents a comprehensive design of a fully integrated multistage GaAs HBT power amplifier that achieves both linearity and high efficiency within a chip area of 0.855 mm2 for 4G and 5G applications covering the lower frequency band of 700-800 MHz. A novel linearizer circuit is integrated to a dual stage class-AB PA to minimize the AM-PM (Amplitude Modulation-Phase Modulation) distortion generated by the parasitic capacitance at the PN-junction under low bias current condition. The linearized power amplifier is able to operate within a 100 MHz linear operating bandwidth (700-800 MHz) while meeting the adjacent channel leakage ratio (ACLR) specification for 4G and 5G application. The fully integrated PA achieves a wideband efficiency of 57.5% at 28.5 dBm output power. Observing a respective input and output return losses of less than 13 dB and 10 dB, the PA delivers a power gain within the range of 34.0-37.0 dB across the operating bandwidth while exhibiting an unconditional stability characteristic from DC up to 5 GHz. The proposed linearization method paves the way of reducing the complexity of linear and high efficiency PA design which is associated with complicated and high-power consumption linearization schemes. © 2013 IEEE

An 0.4-2.8 GHz CMOS Power Amplifier With On-Chip Broadband-Pre-Distorter (BPD) Achieving 36.1-38.6% PAE and 21 dBm Maximum Linear Output Power

A broadband 180 nm CMOS power amplifier (PA) operating from a frequency bandwidth of 400 MHz to 2.8 GHz is presented in this paper. The PA is integrated with an inductor-less Broadband-Pre-Distorter (BPD) to enhance its linearity for wide bandwidth. The BPD consists only of MOS transistors, resistors, and capacitors which contribute to the wideband operation thus independent of the Q factor of passive inductors which contributes to the effectiveness of many other APDs available. The integrated BPD improves the Amplitude Modulation-to-Amplitude Modulation (AM-AM) and Amplitude Modulation-to-Phase Modulation (AM-PM) deviation of the PA across maximum linear output power of 21 dBm. Utilizing a silicon area of 1.69 mm(2), mounted on Roger's RO4000/FR4 PCB, the BPD-PA produces a maximum output power of more than 22 dBm for 2.4 GHz bandwidth with a minimum power gain of 15 dB. The corresponding peak power added efficiency (PAE) of more than 35% is achieved across the operating bandwidth. The fabricated BPD-PA meets the Adjacent Channel Leakage Ratio (ACLR) specification of -30 dBc at a maximum linear output power of 21 dBm (3 dB back-off from maximum output power) when tested with 20 MHz LTE signal at 1.7 GHz

A 53-µA-Quiescent 400-mA Load Demultiplexer Based CMOS Multi-Voltage Domain Low Dropout Regulator for RF Energy Harvester.

Peer reviewed: TrueA low-power capacitorless demultiplexer-based multi-voltage domain low-dropout regulator (MVD-LDO) with 180 nm CMOS technology is proposed in this work. The MVD-LDO has a 1.5 V supply voltage headroom and regulates an output from four voltage domains ranging from 0.8 V to 1.4 V, with a high current efficiency of 99.98% with quiescent current of 53 µA with the aid of an integrated low-power demultiplexer controller which consumes only 68.85 pW. The fabricated chip has an area of 0.149 mm2 and can deliver up to 400 mA of current. The MVD-LDO's line and load regulations are 1.85 mV/V and 0.0003 mV/mA for the low-output voltage domain and 3.53 mV/V and 0.079 mV/mA for the high-output voltage domain. The LDO consumes only 174.5 µW in standby mode, making it suitable for integrating with an RF energy harvester chip to power sensor nodes

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network.

Peer reviewed: TrueThis paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design's robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network.

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design's robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network