Picosecond time measurement using ultra fast analog memories

International audienceThe currently existing electronics dedicated to precise time measurement is mainly based on the use of constant fraction discriminators (CFD) associated with Time to Digital Converters (TDC). The constant fraction technique minimizes the time walk effect (dependency of timing on the pulse amplitude). Several attempts have been made to integrate CFD in multi-channel ASICs. But the time resolution measured on the most advanced one is of the order of 30 ps rms. Two main techniques are used for the TDC architectures. The first one makes use of a voltage ramp started or stopped by the digital pulse. The obtained voltage is converted into digital data using an Analog to Digital Converter (ADC). The timing resolution of such a system is excellent (5 ps rms). But this technique is limited by its large dead time which can be unacceptable for the future high rate experiments. Another popular technique associates a coarse measurement performed by a digital counter with a fine measurement (interpolation) using Delay Line Loop. Such a system can integrate several (8-16) channels on an FPGA or an ASIC. The most advanced DLL-based TDC ASIC exhibits a timing resolution of 25 ps, but only after a careful calibration. It should be noticed that the overall timing resolution is given by the quadratic sum of the discriminator and of the TDC. In the meantime, alternative methods based on digital treatment of the analogue sampled then digitized detector signal have been developed. Such methods permit achieving a timing resolution far better than the sampling frequency. For example, 100ps rms resolution has been reported for a signal sampled at only 100MHz. Digitization systems have followed the progress of commercial ADCs, which currently offer a rate of 500 MHz over 12 bits. Their main drawbacks are the huge output data rate and power consumption. Their packaging, cooling, and tricky clock requirements also makes them very hard to implement. Conversely, high speed analog memories now offer sampling rates far above 1GHz at low cost and with low power consumption. The new USB-WaveCatcher board has been designed to provide high performances over a short time window. It houses on a small surface two 12-bit 500-MHz-bandwidth digitizers sampling between 400 MS/s and 3.2 GS/s. It is based on the patented SAM chip, an analog circular memory of 256 cells per channel. Its innovative matrix design permits reaching these performances, yet in a cheap pure CMOS 0.35µm technology, while consuming only 300 mW. Raw sampling precision is as good as 15ps rms. In an embodiment where the clock is directly sent to the SAM chip, thus limiting the usable sampling frequency to 3.2GHz, and after a calibration of the fixed pattern time distribution, a reproducible time precision of a few ps has been demonstrated. The board also offers various functionalities. Its input offset is tunable over a range of 2 V. It can be triggered either internally or externally and several boards can easily be synchronized. Trigger rates counters are implemented. Both channels can also be used for reflectometry thanks to their internal pulser. The precision obtained for cable length measurements is as good as 2mm. Charge measurement mode is also provided, through integrating on the fly over a programmable time window the signal coming for instance from photo-multipliers. Power consumption is only 2.5 W which permits powering with the sole USB. Signal connectors can be BNC, SMA or LEMO. The board houses a USB 12 Mbits/s interface permitting a dual-channel readout speed of 500 events/s. Faster readout modes are also available. In charge measurement mode, the sustained trigger rate can reach a few tens kHz. A 480Mbits/s version will soon be available. Various evolutions of the SAM chip are under study, targeting either higher precision time measurements or longer time window. The USB-WaveCatcher can thus replace oscilloscopes for a much lower cost in most high-precision short-window applications. Moreover, it opens new doors into the domain of very high precision time measurements

Using ultra fast analog memories for fast photo-detector readout

International audienceThe recent progresses in the field of photo-detection have pushed the performances of the detectors toward the picosecond scale. Currently existing electronics dedicated to precise charge and time measurement is mainly based on the use of high-end oscilloscopes. Numerous test benches are also based on both Charge-to-Amplitude Converters and Constant Fraction Discriminators (CFD) associated with Time to Digital Converters (TDC). The time resolution obtained with some commercial modules is very good (Time to Analog Converters ~ 5 ps rms after amplitude correction), but said modules house very few channels. Some TDC boards offer a higher number of channels, based on a coarse measurement performed by a digital counter associated with a fine measurement (interpolation) using Delay Line Loops, but their overall resolution is only of the order of 30 ps rms. Recently, alternative methods based on digital treatment of the analogue sampled then digitized detector signal have been developed. Such methods permit an easy calculation of the charge and amplitude, and achieve a timing resolution far better than the sampling frequency. Digitization systems have followed the progress of commercial ADCs, but the latter have prohibitory drawbacks like their huge output data rate and power consumption. Conversely, high speed analog memories now offer sampling rates far above 1GHz at low cost and with low power consumption. The new 16-channel WaveCatcher board has been designed to provide high performances over a short time window. It houses sixteen 12-bit 500-MHz-bandwidth digitizers sampling between 400 MS/s and 3.2 GS/s. It is based on the patented SAMLONG ASIC, a high-performance low-power analog circular memory designed in a cheap pure CMOS 0.35µm technology. The board offers a lot of functionalities like smart trigger configurations and embedded charge integration. It houses 480 Mbits/s USB and 1.5Gbits/s optical link interfaces. The board will soon been tested in different test benches dedicated to the characterization of fast MCP-PMTs or SiPMs, but a reproducible time precision better than 10 ps rms has already been demonstrated. The WaveCatcher board thus seems to be a powerful tool for photo-detector characterization and high-scale readout

The SAMPIC Waveform and Time to Digital Converter

Sce ElectroniqueInternational audienceSAMPIC is a Waveform and Time to DigitalConverter (WTDC) multichannel chip. Each of its 16 channelsassociates a DLL-based TDC providing a raw time with an ultrafastanalog memory allowing fine timing extraction as well asother parameters of the pulse. Each channel also integrates adiscriminator that can trigger itself independently or participateto a more complex trigger. After triggering, analog data isdigitized by an on-chip ADC and only that corresponding to aregion of interest is sent serially to the DAQ. The association ofthe raw and fine timings permits achieving timing resolutions of afew ps rms. The paper describes the detailed SAMPIC0architecture and reports its main measured performances

Development of a sampling ASIC for fast detector signals

International audienceIn the context of the Large Area Picosecond Photodetector (LAPPD) pro ject the motivation to measure time-of-flight at the picosecond reso- lution has pushed towards a faster signal rise-time (below 100 ps) and a higher bandwidth output (higher than 1 GHz) detector, thus, leading to a new signal development and integrity studies of Micro-Channel Plates (MCP) photo-detectors. Similarly, the signal path, is being simulated and characterized, from the anodes to the input of the readout electronics, to minimise losses. Furthermore, to acquire the detector fast pulses a new 10 Gs/s high input bandwidth, 130 nm CMOS sampling chip is being de- veloped

Study of timing characteristics of a 3 m long plastic scintillator counter using waveform digitizers

A plastic scintillator bar with dimensions 300 cm x 2.5 cm x 11 cm was exposed to a focused muon beam to study its light yield and timing characteristics as a function of position and angle of incidence. The scintillating light was read out at both ends by photomultiplier tubes whose pulse shapes were recorded by waveform digitizers. Results obtained with the WAVECATCHER and SAMPIC digitizers are analyzed and compared. A discussion of the various factors affecting the timing resolution is presented. Prospects for applications of plastic scintillator technology in large-scale particle physics detectors with timing resolution around 100 ps are provided in light of the results

SCTA - A Rad-Hard BiCMOS Analogue Readout ASIC for the ATLAS Semiconductor Tracker

Two prototype chips for the analogue readout of silicon strip detectors in the ATLAS Semiconductor Tracker (SCT) have been designed and manufactured, in 32 channels and 128 channel versions, using the radiation hard BiCMOS DMILL process. The SCTA chip comprises three basic blocks: front-end amplifier, analogue pipeline and output multiplexer. The front-end circuit is a fast transresistance amplifier followed by an integrator, providing fast shaping with a peaking time of 25 ns, and an output buffer. The front end output values are sampled at 40 MHz rate and stored in a 112-cell deep analogue pipeline. The delay between the write pointer and trigger pointer is tunable between 2 ms and 2.5 ms. The chip has been tested successfully and subsequently irradiated up to 10 Mrad. Full functionality of all blocks of the chip has been achieved at a clock frequency of 40 MHz both before and after irradiation. Noise figures of ENC = 720 e- + 33 e-/pF before irradiation and 840 e- + 33 e-/pF after irradiation have been obtained

The Micromegas detector of the CAST experiment

A low background Micromegas detector has been operating in the CAST experiment at CERN for the search of solar axions during the first phase of the experiment (2002-2004). The detector, made out of low radioactivity materials, operated efficiently and achieved a very low level of background rejection (5 x 10^-5 counts/keV/cm^2/s) without shielding.Comment: 13 pages, 12 figures and images, submitted to New Journal o

AFTER, the front end ASIC of the T2K Time Projection Chambers

The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan. A near detector, located at 280m of the production target, is used to characterize the beam. One of its key elements is a tracker, made of three Time Projection Chambers (TPC) read by Micromegas endplates. A new readout system has been developed to collect, amplify, condition and acquire the data produced by the 124,000 detector channels of these detectors. The front-end element of this system is a a new 72-channel application specific integrated circuit. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency, shaping time, gain, while taking advantage of the low physics events rate of 0.3 Hz. We detail the design and the performance of this ASIC and report on the deployment of the frond-end electronics on-site