Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs

The reliability of multiprocessor system-on-chips (MPSoCs) is nowadays threatened by high chip temperatures leading to long-term reliability concerns and short-term functional errors. High chip temperatures might not only cause potential deadline violations, but also increase cooling costs and leakage power. Pro-active thermal-aware allocation and scheduling techniques that avoid thermal emergencies are promising techniques to reduce the peak temperature of an MPSoC. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is time-consuming, in particular for unknown input patterns and data. In this paper, we address this challenge and present a fast analytic method to calculate a non-trivial upper bound on the maximum temperature of a multi-core real-time system with non-deterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighboring cores and temperature-dependent leakage power. Afterwards, we integrate the proposed thermal analysis method into a design-space exploration framework to optimize the task to processing component assignment. Finally, we apply the proposed method in various case studies to explore thermal hot spots and to optimize the task to processing component assignmen

Real-time worst-case temperature analysis with temperature-dependent parameters

With the evolution of today's semiconductor technology, chip temperature increases rapidly mainly due to the growth in power density. Therefore, for modern embedded real-time systems it is crucial to estimate maximal temperatures early in the design in order to avoid burnout and to guarantee that the system can meet its real-time constraints. This paper provides answers to a fundamental question: What is the worst-case peak temperature of a real-time embedded system under all feasible scenarios of task arrivals? Anovel thermal-aware analytic framework is proposed that combines a general event/resource model based on network and real-time calculus with system thermal equations. This analysis framework has the capability to handle a broad range of uncertainties in terms of task execution times, task invocation periods, jitter in task arrivals, and resource availability. The considered model takes both dynamic and leakage power as well as thermal dependent conductivity into consideration. Thorough simulation experiments validate the theoretical result

Evaluation des performances pour les systèmes embarqués hétérogènes, multiprocesseur monopuces

Les systèmes embarqués multiprocesseur monopuces (Multi-Processor System-on-Chip, MPSoC) visent l'intégration des sous-systèmes variés, matériels et logiciels, sur une seule puce. Ainsi, l'hétérogénéité et les contraintes imposées pour la mise sur le marché rendent l'analyse en vue de l'évaluation des performances et de l'optimisation de ces systèmes très complexes. L'évaluation des performances est une étape clef dans n'importe quel flot de conception. En se basant sur les résultats de l'évaluation des performances, il est possible de prendre des décisions et de réaliser des compromis pour l'optimisation du système global. La littérature prouve qu'une grande partie du temps de conception est passée dans l'évaluation des performances. De plus, les itérations dans le flot de conception deviennent prohibitives pour des systèmes complexes. Par conséquent, la réalisation des MPSoCs à rendement élevé est un défi. La solution est fortement liée à la disponibilité des méthodes rapides et précises pour l'évaluation des performances. Dans cette thèse, le terme performances est limité aux performances des temps d'exécution pour la réalisation finale du système. L'aspect temporel est intensivement analysé pour la validation des systèmes temps-réel et l'optimisation des sous-ensembles d'interconnexion. Nous avons également considéré la vitesse de la méthode proposée d'évaluation des performances, car les temps d'évaluation peuvent devenir prohibitifs pour des systèmes MPSoC complexes. Notre principale contribution est de définir une méthodologie globale d'évaluation des performances pour les systèmes MPSoC. Nous avons également orienté notre recherche vers les performances de l'exécution du logiciel. On a considéré l'évaluation des performances pour un modèle de haut niveau d'abstraction, afin d'avoir une vitesse élevée d'évaluation. De plus, on a inclus des annotations des temps d'exécution, afin d'avoir une bonne précision d'évaluation.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Timed HW-SW Cosimulation Using Native Execution of OS and Application SW

We present a method of timed HW-SW cosimulation which uses native execution of OS and application SW. The method presents fast and accurate cosimulation. Since the OS and application SW are executed natively on the simulation host, it gives faster simulation than the case when an instruction set simulator is used. Compared to the conventional usage of native execution of OS and application SW, it presents more accurate simulation since it allows for timing simulation of OS and application SW and it can be incorporated into timed HW-SW cosimulation. We present the details of building such a fast and accurate SW simulation mode

Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs

ISSN:0923-8174ISSN:1573-072

ChronoSym: a new approach for fast and accurate SoC cosimulation

The early validation of modern SoC is not anymore feasible using traditional cycle-accurate cosimulations. These are based on the concurrent execution between SW running on multiple Instruction Set Simulators and HW simulators. The challenge is then speeding-up the simulation, without sacrificing the accuracy of traditional methods. The key contribution of this paper is a novel fast and accurate HW/SW cosimulation approach, allowing to handle large SoCs, while reducing the design cycle. The key underlying concepts are timed native SW execution, combined with detailed HW/SW interaction models. This approach is implemented in ChronoSym tool and applied to two real SoC applications