Managing Conflict: Reconciling Being Always-On and Concurrent Desire to Protect Personal Information –A Mixed Methods Study of Connected Consumer

Poster Presentation at the Engaged Management Scholarship Conference, Philadelphia, PA, September 6-8, 2018. Case Western Reserve University, Cleveland, O

Double-channel hemt device and manufacturing method thereof

An HEMT device (1), comprising: a semiconductor body (15) including a heterojunction structure (13); a dielectric layer (7) on the semiconductor body; a gate electrode (8); a drain electrode (12), facing a first side (8') of the gate electrode (8); and a source electrode (10), facing a second side (8") opposite to the first side (8') of the gate electrode; an auxiliary channel layer (20), which extends over the heterojunction structure (13) between the gate electrode (8) and the drain electrode (12), in electrical contact with the drain electrode (12) and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

Experimental and Numerical Evaluation of RON Degradation in GaN HEMTs during Pulse-Mode Operation

The on-resistance (RON) degradation in normally-OFF GaN high electron mobility transistors has been evaluated both experimentally and by means of numerical simulations by analyzing its drift during device pulse-mode operation. Experimental data showed that the device RON measured during the on-time interval of the switching period increased with time resulting in a thermally activated process with an activation energy $EA=0.83$ eV. For the first time, numerical simulations have been carried out in order to evaluate the device RON drift during pulse-mode operation and to understand the physical phenomena involved. A good qualitative agreement between experimental and simulated data has been obtained when considering in the simulated device simply a hole trap located at 0.83 eV from the GaN valence-band, an energy level which has been linked in previous works to carbon-doping within the GaN buffer

EXPERIMENTAL EVALUATION OF PERFORMANCES OF DIFFERENT SOLUTIONS OF FINISHING FOR MASONRY BUILDINGS FOR DETERMINING DURABILITY

The components of the building envelopes have to provide performances of different types: it is supposed to resist to the weather agents, to have a good water vapor permeability in order to prevent some degradation phenomena, and to inhibit the capillary rising dampness. But it must also maintain all these features over the time, in other words it must have a high durability. The designers, when they have to choose finishing solutions, are put in front of very complex evaluations, with the aim of finding the most appropriate one, given the specific context stress factors. To provide a useful guide for those frequent situations, two Departments of University of Naples Federico II conducted combined tests in the laboratories and on the field, on four types of finishing solutions (plaster + painting) for tuff masonry, which is typical of Southern Italy. In the DICMAPI laboratory the specimens were subjected to tests of water absorption by capillarity, tests of water vapor permeability, tests of water absorption at a low pressure, and tests of accelerated aging in a QUV machine. The field assessments were carried out on 500 sampled buildings in the city of Naples, over 10 years of monitoring, showing the different behavior of the four types of selected specimens: for example, the characteristics of the finishing solutions of macroporous plaster + silicate paint and cement plaster + quartz paint have remained almost the same, without significant performance decay. The results could represent a good starting point for the creation of a useful handbook for designers of recovery interventions

Hemt transistor including field plate regions and manufacturing process thereof

HEMT transistor (50; 100; 150) having a semiconductor body (52) forming a semiconductive heterostructure (54, 56); a gate region (60), of conductive material, arranged above and in contact with the semiconductor body (52); a first insulating layer (58) extending above the semiconductor body, laterally to the conductive gate region (60); a second insulating layer (62) extending above the first insulating layer (58) and the gate region (60); a first field plate region (84), of conductive material, extending between the first and the second insulating layers (58), laterally spaced from the conductive gate region (60); and a second field plate region (85), of conductive material, extending above the second insulating layer (62), vertically aligned with the first field plate region (84)

Double-channel hemt device and manufacturing method thereof

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

Double-channel hemt device and manufacturing method thereof

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

Double-channel HEMT device and manufacturing method thereof

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

High electron mobility transistor and manufacturing method thereof

HEMT (1; 21; 31; 51) including a buffer layer (4), a hole-supply layer (6) on the buffer layer (4), a heterostructure (7) on the hole-supply layer (6), and a source electrode (16). The hole-supply layer (6) is made of P-type doped semiconductor material, the buffer layer (4) is doped with carbon, and the source electrode (16) is in direct electrical contact with the hole-supply layer (6), such that the hole-supply layer (6) can be biased to facilitate the transport of holes from the hole-supply layer (6) to the buffer layer (4)