Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Variability and Reliability of Graphene Field-Effect Transistors with CaF2 Insulators

Graphene is a promising material for applications as a channel in graphene field-effect transistors (GFETs) which may be used as a building block for optoelectronics, high-frequency devices and sensors. However, these devices require gate insulators which ideally should form atomically flat interfaces with graphene and at the same time contain small densities of traps to maintain high device stability. Previously used amorphous oxides, such as SiO2 and Al2O3, however, typically suffer from oxide dangling bonds at the interface, high surface roughness and numerous border oxide traps. In order to address these challenges, here we use for the first time 2nm thick epitaxial CaF2 as a gate insulator in GFETs. By analyzing device-to-device variability for over 200 devices fabricated in two batches, we find that tens of them show similar gate transfer characteristics. Our statistical analysis of the hysteresis up to 175C has revealed that while an ambient-sensitive counterclockwise hysteresis can be present in some devices, the dominant mechanism is thermally activated charge trapping by border defects in CaF2 which results in the conventional clockwise hysteresis. We demonstrate that both the hysteresis and bias-temperature instabilities in our GFETs with CaF2 are comparable to similar devices with SiO2 and Al2O3. In particular, we achieve a small hysteresis below 0.01 V for equivalent oxide thickness (EOT) of about 1 nm at the electric fields up to 15 MV/cm and sweep times in the kilosecond range. Thus, our results demonstrate that crystalline CaF2 is a promising insulator for highly-stable GFETs

Characterization and modeling of charged defects in silicon and 2D field-effect transistors

Zusammenfassung in deutscher SpracheTitelübersetzung des Autors: Charakterisierung und Modellierung von Defekten in Silizium und 2D FeldeffekttransistorenThis work has been conducted at a time when scaling of Si MOSFETs according to Moore's Law is close to its end. Hence, the research focus is shifting from nanoscale Si MOSFETs to nextgeneration transistors based on 2D materials. Although these technologies are dramatically different from one another, the question of reliability is essential for both types of devices. However, the typical dimensions of modern nanoscale SiMOSFETs are already far below 100 nm, while the channel lengths of next-generation 2D FETs are still in micrometer range. Hence, in the former case the reliability is dominated by single discrete defects and in the latter case one has to deal with the impact of continuously distributed defects. In the course of this dissertation we characterize the reliability of both nanoscale Si MOSFETs and next-generation 2D FETs with graphene and molybdenum disulphide (MoS2) channels. First we study the impact of charged traps and random dopants on the performance of nanoscale Si MOSFETs. Based on the results of TCAD simulations, we introduce a precise technique which allows for evaluation of the lateral trap position from the experimental data obtained using time-dependent defect spectroscopy. While our method fully accounts for the impact of random dopants, the typical uncertainty is several percents of the channel length. Next we switch our attention to graphene FETs and analyze their reliability with respect to bias-temperature instabilities (BTI) and hot carrier degradation (HCD). Our analysis shows that the degradation/recovery dynamics of BTI and some HCD mechanisms can be captured using the models previously developed for Si technologies. Also, we show that HCD in graphene FETs can either accelerate or suppress BTI degradation, depending on the bias condition. In some cases this leads to a non-trivial impact on charged trap density and carrier mobility, both of which are correlated to each other. Finally, we study the reliability of MoS2 FETs, which are more suitable for applications in digital circuits compared to graphene transistors. While analyzing the hysteresis and BTI in these devices, we demonstrate that our MoS2 FETs are more stable compared to their previously reported counterparts. Moreover, we show that use of hexagonal boron nitride as a gate insulator significantly improves the reliability of MoS2 FETs, especially at low temperatures. Lastly, we introduce the proof of concept for modeling of the reliability characteristics of MoS2 FETs using advanced simulation software previously developed for Si MOSFETs. The results obtained for 2D FETs allow for a general understanding of their reliability at the beginning stage of research. However, sooner or later circuit integration of these new devices will request considerable scaling of their dimensions and dramatical improvement of the technology level. As so, reliability of 2D FETs will be also dominated by single defects. Thus, we can expect that our trap location technique developed for nanoscale Si MOSFETs, as well as the described modeling approach, can be applied for next-generation 2D FETs in future.12