Sulfuric acid and hydrogen peroxide surface passivation effects on AlGaN/GaN high electron mobility transistors

In this work, we have compared SiNx passivation, hydrogen peroxide, and sulfuric acid treatment on AlGaN/GaN HEMTs surface after full device fabrication on Si substrate. Both the chemical treatments resulted in the suppression of device pinch-off gate leakage current below 1 μA/mm, which is much lower than that for SiNx passivation. The greatest suppression over the range of devices is observed with the sulfuric acid treatment. The device on/off current ratio is improved (from 104–105 to 107) and a reduction in the device sub-threshold (S.S.) slope (from ∼215 to 90 mV/decade) is achieved. The sulfuric acid is believed to work by oxidizing the surface which has a strong passivating effect on the gate leakage current. The interface trap charge density (Dit ) is reduced (from 4.86 to 0.90 × 1012 cm−2 eV−1), calculated from the change in the device S.S. The gate surface leakage current mechanism is explained by combined Mott hopping conduction and Poole Frenkel models for both untreated and sulfuric acid treated devices. Combining the sulfuric acid treatment underneath the gate with the SiNx passivation after full device fabrication results in the reduction of Dit and improves the surface related current collapse

Field plate designs in all-GaN cascode heterojunction field-effect transistors

Different source field plate (FP) connections are compared for the all-GaN integrated cascode device to address the capacitance matching and turn-off controllability issues reported in the conventional GaN plus Si cascode. The experimental results suggest that the cascode device with an FP connected to the source terminal can significantly suppress the off-state internode voltage, leading to minimized capacitive energy loss and reduced overvoltage stress at the internode. This is attributed to the reduced ratio of the drain-source capacitance of the depletion mode cascode part to the total capacitance at the cascode internode. An additional FP on the E-mode cascode part is proposed to further suppress the off-state internode voltage and benefit the device. Cascode devices with the source FP connecting to the enhancement mode gate have an improved switching controllability via gate resistance during turn-off and hence enhanced dv/dt immunity in the drain loop

Effects of surface plasma treatment on threshold voltage hysteresis and instability in metal-insulator-semiconductor (MIS) AlGaN/GaN heterostructure HEMTs

In a bid to understand the commonly observed hysteresis in the threshold voltage (VTH) in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors during forward gate bias stress, we have analyzed a series of measurements on devices with no surface treatment and with two different plasma treatments before the in-situ Al2O3 deposition. The observed changes between samples were quasi-equilibrium VTH, forward bias related VTH hysteresis, and electrical response to reverse bias stress. To explain these effects, a disorder induced gap state model, combined with a discrete level donor, at the dielectric/semiconductor interface was employed. Technology Computer-Aided Design modeling demonstrated the possible differences in the interface state distributions that could give a consistent explanation for the observations

Designed multifunctional polymeric nanomedicines: long-term biodistribution and tumour accumulation of aptamer-targeted nanomaterials

We report a novel multifunctional hyperbranched polymer based on polyethylene glycol (PEG) as a nanomedicine platform that facilitates longitudinal and quantitative 89Zr-PET imaging, enhancing knowledge of nanomaterial biodistribution and pharmacokinetics/pharmacodynamics both in vivo and ex vivo. Anti-VEGF-A DNA aptamer functionalization increased tumour accumulation by >2-fold in a breast cancer model

Enhancement-mode metal-insulator-semiconductor GaN/AlInN/GaN heterostructure field-effect transistors on Si with a threshold voltage of +3.0V and blocking voltage above 1000V

Enhancement-mode AlInN/GaN metal–insulator–semiconductor heterostructure field-effect transistors on silicon are reported. A fluorine-based plasma treatment and gate dielectric are employed, and the devices exhibit a threshold voltage of +3 V. A drain current density of 295 mA/mm for a gate bias of +10 V is measured. An excellent off-state blocking voltage capability of 630 V for a leakage current of 1 µA/mm, and over 1000 V for 10 µA/mm are achieved on a 20-µm-gate–drain separation device at gate bias of 0 V. The dynamic on-resistance is ~2.2 times the DC on-resistance when pulsing from an off-state drain bias of 500 V