A Low Level Component Model enabling Resource Specialization of HPC Applications

Scientific applications are still getting more complex, e.g. to improve their accuracy by taking into account more phenomena. Moreover, computing infrastructures are continuing their fast evolution. Therefore, software engineering is becoming a major issue to achieve easiness of development, portability, simple maintenance, while achieving high performance. Software component model is a promising approach, which enables to manipulate the software architecture of an application. However, existing models do not capture enough resource specificities. This paper proposes a low level component model (L2C) that supports directly native connectors such as MPI, shared memory and method invocation. L2C is intended to be used as a back end by a ''compiler'' (such as HLCM) to generate an application assembly specific to a given machine. This paper shows on a typical domain decomposition use case that \llc can achieve the same performance as native implementations, while gaining benefits such as enabling resource specialization capabilities.Les applications scientifiques continuent de devenir de plus en plus complexes, par exemple pour améliorer leur précision en intégrant davantage de phénomènes à simuler. Par ailleurs, les infrastructures de calcul continuent leur rapide évolution. Ainsi, l'ingénierie logicielle devient un défi très important afin de permettre une facilité de développement, la portabilité des codes, et une maintenance acceptable tout en permettant de hautes performances. Les modèles de composants logiciels offrent une approche prometteuse en permettant de manipuler l'architecture logicielle d'une application. Cependant, les modèles existant ne permettent pas de capturer suffisamment les spécificités des ressources de calcul. Cet article propose un modèle de composant logiciel ''bas niveau'' (L2C) qui permet l'intègration native de connecteurs tels que MPI, la mémoire partagée ou l'invocation de méthode. L2C est destiné à être utilisé en tant que langage de sortie d'un ''compilateur'' (tel que HLCM) générant un assemblage d'une application spécifique à une machine et à une exécution. Cet article montre sur un cas d'étude typique de décomposition de domaines que L2C permet d'atteindre les même performances que les applications natives, tout en offrant des possibilités d'optimisation par rapport aux capacités des ressources

Performance Evaluation and Tuning of 2D Jacobi Iteration on Many-core Machines

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Auto-tuning 2D Stencil Applications on Multi-core Parallel Machines

PRACE 2IP White PaperOn multi-core clusters or supercomputers, how to get good performance when running high performance computing (HPC) applications is a main concern. In this report, performance oriented auto-tuning strategies and experimental results are presented for stencil HPC applications on multi-core parallel machines. A typical 2D Jacobi benchmark is chosen as the experimental stencil application. The main tuning strategies include data partitioning within a multi-core node, number of threads within a multi-core node, data partitioning for a number of nodes, number of nodes in a multi-core cluster system. The results of the experiments are based on multi-core parallel machines from PRACE or Grid'5000, such as Curie, and Stremi cluster

A low level component model easing performance portability of HPC applications

International audienceScientific applications are getting increasingly complex, e.g., to improve their accuracy by taking into account more phenomena. Meanwhile, computing infrastructures are continuing their fast evolution. Thus, software engineering is becoming a major issue to offer ease of development, portability and maintainability while achieving high performance. Component based software engineering offers a promising approach that enables the manipulation of the software architecture of applications. However, existing models do not provide an adequate support for performance portability of HPC applications. This paper proposes a low level component model (L²C) that supports inter-component interactions for typical scenarios of high performance computing, such as process-local shared memory and function invocation (C++ and Fortran), MPI, and Corba. To study the benefits of using L²C, this paper walks through an example of stencil computation, i.e. a structured mesh Jacobi implementation of the 2D heat equation parallelized through domain decomposition. The experimental results obtained on the Grid'5000 testbed and on the Curie supercomputer show that L²C can achieve performance similar to that of native implementations, while easing performance portability

A 65-nm CMOS P-well/Deep N-well Avalanche Photodetector for Integrated 850-nm Optical

A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a 3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps

A Low Level Component Model Enabling Performance Portability of HPC Applications

International audienceScientific applications are increasingly getting complex, e.g. to improve their accuracy by taking into account more phenomena. Meanwhile, computing infrastructures are continuing their fast evolution. Thus, software engineering is becoming a major issue to achieve easiness of development, portability, maintenance, while achieving high performance. Software component model is a promising approach, which enables to manipulate the software architecture of an application. However, existing models do not provide enough support for performance portability. This paper proposes a low level component model (L2 C) that supports directly native connectors for typical scenarios of high performance computing, such as MPI, shared memory and method invocation. We walk through a typical example of stencil compu tation, i.e. 2-D Jacobi computation with domain decomposition. The experimental results show that L2 C can achieve the same p erformance as native implementations, while gaining benefits such as performance portability on the basis of the software com ponent model

A 25-Gb/s 32.1-dB CMOS Limiting Amplifier for Integrated Optical Receivers

A 65-nm CMOS limiting amplifier based on three stages of a modified Cherry-Hooper amplifier with offset cancellation is presented. The trade-off between the offset cancellation range and input-referred noise is discussed. The variations on gain and bandwidth due to PVT corners are presented. The limiting amplifier achieves 32.1 dB gain and 21.6 GHz bandwidth, with a 1-V supply and a power dissipation of 33.3 mW

Integrated CMOS photodetectors for short-range optical communication

This paper presents the measured performance of different photodetector (PD) structures in a standard 65-nm CMOS technology. All photodiodes and phototransistors are tested using an 850-nm laser source through a 62.5-μm-diameter multi-mode fiber. Measurement and simulation results show that integrated CMOS photodetector with proper equalization can support > 10 Gbps systems. © 2013 IEEE