The Impact of Submicron 10x Reticle Defects on Images Printed with a 0.28 NA G-Line Stepper

A lOX reticle was produced with programmed defects of both polarities varying size, proximity to adjacent features, and feature sizes. The defects were imaged in various resist materials over silicon, silicon dioxide, silicon nitride, polysilicon, aluminum, and a 1X chrome mask using a GCA/Mann 4800 stepper. Results obtained using optical and scanning electron microscopy demonstrated that reticle defects as small as 1.0 micron, when in proximity to a feature, will cause linewidth variation in the printed image. The resist film and underlying substrate did affect the linewidth variation. Defocus and over/under exposure also influenced the severity of damage created by reticle defects. A two—dimensional aerial image simulator SPLAT, which is a version of SAMPLE, was used to simulate the optical interactions of defects with adjacent features

Process development of an analog/digital mixed-mode BiCMOS system at RIT

The development of an analog/digital mixed-mode BiCMOS process is presented. The process uses the RIT factory n-well CMOS process as its baseline process. The process is tailored to meet the requirements of an analog/digital system, while minimizing process complexity and maximizing compatibility with the established CMOS process. The process development includes determining the device requirements for the BiCMOS process, evaluating the established CMOS process, and integrating the additional process steps into the baseline process. TMA SUPREM III 1-D Process Analysis Program and RIT\u27s processing history are used as guidelines, keeping manufacturability an important issue. An integrated test chip is developed to measure the performance of the process and to compare measured results with modelling simulations. The test chip includes test structures for each masking level, along with test circuits that are designed using CMOS, bipolar, and BiCMOS technologies, which perform analog and digital functions. The process is implemented into the RIT factory, utilizing the WIPTRACK tracking system. Each processing step is entered into the system with complete instructions. Real-time measurement data is entered into the system at each step by operators under the supervision of the process engineer. Analysis of the test structures and test circuits will demonstrate the performance of the designed process

Flash lamp annealed polycrystalline silicon as a potential candidate for large panel manufacturing

The flat-panel display industry is in pursuit of TFT manufacturing processes which are cost-effective, easily scalable to large glass panels, and meet the performance requirements of advanced display products. While excimer laser anneal (ELA) low-temperature polycrystalline silicon (LTPS) can offer exceptional TFT performance, a lower grade LTPS may still satisfy product requirements at a lower production cost. Flash-Lamp Annealing (FLA) is an emerging candidate for the manufacture of LTPS. Multi-lamp exposure systems with high repetition pulse rates would potentially offer significant advantages in manufacturing throughput and cost over ELA. Techniques to overcome challenges that have hindered device scaling and reduction in variation of device operation are under investigation. The following presents a status update on the development of FLA Polycrystalline Silicon (FLAPS) technology. The FLA equipment used for this work was a NovaCentrix PulseForge 3300 system, capable of uniform exposure of a 7 cm x 12 cm area at intensities as high as 50 kW/cm2 over microseconds pulse duration. PMOS TFTs were fabricated using combinations of FLA, ion implantation and furnace annealing to define the source/drain and channel regions. Predefined polygons of 60 nm thick amorphous silicon vertically sandwiched between layers of SiO2 were crystallized on Corning Lotus NXT display glass using single-pulse FLA exposure. The amorphous silicon melts while absorbing a sufficient fraction of the xenon emission spectrum, and becomes polycrystalline while staying within the thermal constraints of the underlying glass substrate. Boron dopant ions were implantation into the source/drain regions defined by lithographic patterning or a self-aligned gate strategy. Boron activation was realized by combinations of FLA, furnace annealing, and pre-amorphization using an electrically inactive species. FLA conditions following dopant introduction avoided silicon melting which causes significant lateral diffusion. Representative electrical characteristics are shown in figure 1. While the device operation demonstrates a general dependence on the degree of dopant activation, observations on the electrical characteristics indicate a complex relationship between defect states and the specific implant/activation strategy applied. The influence of doping strategy on both device performance and resistance to failure is the primary focus of this work. Additional experiments involving variations in the FLAPS morphology will also be discussed. Please click Additional Files below to see the full abstract

Donor activation in boron and phosphorus implanted self-aligned bottom-gate Igzo Tfts

Self-aligned channel regions in thin-film transistors (TFTs) have advantages in reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. A common method used to fabricate self-aligned a‑Si:H TFTs is to utilize a through-glass exposure of photoresist which is blocked by the opaque metal bottom-gate electrode [1,2]. This process does not require an additional photomask or lithographic alignment, and thus supports low production cost. Sputtered IGZO has been introduced into flat panel display product manufacturing, exhibiting a channel mobility of approximately an order of magnitude higher than a-Si:H. The working source/drain electrodes in IGZO TFTs can be direct metal contact regions to the IGZO, without the need for additional processes such as doping to render the IGZO conductive. Proper metallurgy and annealing processes can provide ohmic behavior with minimal series resistance, however this usually requires several microns of gate-to-source/drain overlap to ensure such behavior. Please click Download on the upper right corner to see the full abstract

Instances and connectors : issues for a second generation process language

This work is supported by UK EPSRC grants GR/L34433 and GR/L32699Over the past decade a variety of process languages have been defined, used and evaluated. It is now possible to consider second generation languages based on this experience. Rather than develop a second generation wish list this position paper explores two issues: instances and connectors. Instances relate to the relationship between a process model as a description and the, possibly multiple, enacting instances which are created from it. Connectors refers to the issue of concurrency control and achieving a higher level of abstraction in how parts of a model interact. We believe that these issues are key to developing systems which can effectively support business processes, and that they have not received sufficient attention within the process modelling community. Through exploring these issues we also illustrate our approach to designing a second generation process language.Postprin

Liberalization, globalization and the dynamics of democracy in India

In the closing decades of the twentieth century there has been an almost complete intellectual triumph of the twin principles of marketization (understood here as referring to the liberalization of domestic markets and freer international mobility of goods, services, financial capital and perhaps, more arguably, labour) and democratization . A paradigm shift of this extent and magnitude would not have occurred in the absence of some broad consensus among policymakers and (sections of) intellectuals around the globe on the desirability of such a change. There seems to be a two-fold causal nexus between marketization and democracy. The first is more direct, stemming from the fact of both systems sharing certain values and attitudes in common. But there is also a second more indirect chain from marketization to democracy, which is predicated via three sub-chains (i) from marketization to growth, (ii) from growth to overall material development welfare and (iii) from material development to social welfare and democracy. We examine each of these sub-links in detail with a view to obtaining a greater understanding of the hypothesized role of free markets in promoting democracies. In the later part of the paper we examine the socio-economic outcomes governing the quality of democracy in a specifically Indian context