Low power multicarrier- code division multiple access receiver on field programmable gate array

This paper presents a low power multi-carrier code division multiple access (MC-CDMA) receiver on field-programable gate array (FPGA). Most of the wireless application nowadays such as wireless sensor networks, portable computation and many more require a low power design. Time-division multiple access (TDMA) is used in most wireless receivers are not very efficient since they adopt scheduling technique. The first objective of this paper is to design and verify a low power MC-CDMA receiver and the second objective is to implement the MC-CDMA receiver on FPGA. MC-CDMA act as a processor with the ability to process transmit or receive data simultaneously over a single communication channel. The MC-CDMA design in this paper consists of pipelined FFT and combiner. The primary purpose of pipelined FFT plus combiner module in this research is to execute the instruction on communication (data send and receive) and self-organization. Besides these two modules, there is a memory for temporarily storing the data and an internal clock, among other things. To accomplish these, the designs have been carried out using Verilog coding in Modelsim software, and the design verifications are done through Matlab. The design implementation is via Quartus and on DE2-115 Altera FPGA board. The functionality analyses have been carried out on simulation, and the hardware implementation of the MC-CDMA receiver is tested. Both simulation and hardware execution are successful where the receiver received and displayed the output accordingly. MC-CDMA achieves 39.13mW total power consumption

The impact of M-ary rates on various quadrature amplitude modulation detection

The 5G system-based cognitive radio network is promised to meet the requirements of huge data applications with spectrum. However, the M-ary effect on the detection has not been thoroughly investigated. In this paper, an M-ary of quadrature amplitude modulation detection system is studied. Many rates are used in this study 4, 16, 64, and 256 constellation points. The detection system is applied to cooperative spectrum sensing to enhance the performance of detection for various rates of M-ary with low signal-to-noise ratio (SNR). Further, three kinds of signals based 5G system are sensed: filtered-orthogonal frequency division multiplexing (F-OFDM), filter bank multi-carrier (FBMC), and universal filtered multi-carrier (UFMC). The best detection performance is obtained when the M-ary=4 and number of SUs=50 user, whereas the worst detection performance is obtained when the M-ary=256 and number of SUs=10 user, as revealed in the simulation results. In addition, the detection performance for the F-OFDM signal is better than that of UFMC and FBMC signals for SNR <0 dB

Identification of distributed denial of services anomalies by using combination of entropy and sequential probabilities ratio test methods

One of the most dangerous kinds of attacks affecting computers is a distributed denial of services (DDoS) attack. The main goal of this attack is to bring the targeted machine down and make their services unavailable to legal users. This can be accomplished mainly by directing many machines to send a very large number of packets toward the specified machine to consume its resources and stop it from working. We implemented a method using Java based on entropy and sequential probabilities ratio test (ESPRT) methods to identify malicious flows and their switch interfaces that aid them in passing through. Entropy (E) is the first technique, and the sequential probabilities ratio test (SPRT) is the second technique. The entropy method alone compares its results with a certain threshold in order to make a decision. The accuracy and F-scores for entropy results thus changed when the threshold values changed. Using both entropy and SPRT removed the uncertainty associated with the entropy threshold. The false positive rate was also reduced when combining both techniques. Entropy-based detection methods divide incoming traffic into groups of traffic that have the same size. The size of these groups is determined by a parameter called window size. The Defense Advanced Research Projects Agency (DARPA) 1998, DARPA2000, and Canadian Institute for Cybersecurity (CIC-DDoS2019) databases were used to evaluate the implementation of this method. The metric of a confusion matrix was used to compare the ESPRT results with the results of other methods. The accuracy and f-scores for the DARPA 1998 dataset were 0.995 and 0.997, respectively, for the ESPRT method when the window size was set at 50 and 75 packets. The detection rate of ESPRT for the same dataset was 0.995 when the window size was set to 10 packets. The average accuracy for the DARPA 2000 dataset for ESPRT was 0.905, and the detection rate was 0.929. Finally, ESPRT was scalable to a multiple domain topology application

Low power fast fourier transform and combiner of multi carrier-code division multiple access receiver system for wireless sensor networks

This thesis presents a low power fast Fourier transforms (FFT) and combiner of multi-carrier code division multiple access (MC-CDMA) receiver for wireless sensor networks (WSN). WSN is a system comprises of sensor nodes with data sampling, data processing, and communication capabilities. In WSN, there is the need for scheduling of various communication activities between sensor nodes to the cluster-head or the neighbouring nodes. Most of the WSN adapt the time division multiple access (TDMA) and media access control (MAC) layer approach techniques for scheduling purposes. The main question was how to ensure the channel is most productive when the sensor nodes have the urge to transmit the data available but cannot because of the scheduling protocol adapted by the WSN. Besides, scheduling contributes to higher power consumption for sensor nodes in WSN, reducing the sensor nodes lifetime. This research is motivated by the desire to eliminate scheduling in the WSN communication protocol with low power MC-CDMA system designs. MC-CDMA offers a collision-free medium since MC-CDMA can process transmit or receive data simultaneously over a single communication channel. Most of the sensor nodes are battery operated and sometimes placed in an isolated area, making it difficult to change the battery or connect to a direct power supply. Thus, the design must be in low power for longer lifespan of the nodes. In this research, different point (16, 64, and 256-point) and radixes (radix-4 and radix-8) FFT module, and combiner module are considered and analysed. Integration of both modules forms the MC-CDMA receiver. Pipelined FFT function is to convert signal in the time domain to the frequency domain, while combiner performs despreading, channel estimation and data demodulation to recover the transmitted bits. The low power designs in MC-CDMA have been carried out using Verilog coding in Modelsim software, and the design verifications are done through Matlab. The design implementation is via Quartus and programmed on DE2-115 Altera field-programmable gate array (FPGA) board. Synopsys is used for power and area consumption studies with 90nm CMOS Technology. The functionality analyses have been carried out on simulation, and the hardware implementation of the MC-CDMA receiver is tested to see the MC-CDMA receiver ability to received data without scheduling. Both simulation and hardware execution are successful where the receiver received and displayed the output accordingly. MC-CDMA achieves 39.13mW power consumption and 0.95mm2 design area consumption. Signal-to-noise (SNR) module was implemented on the receiver, and the results show that average SNR for MC-CDMA receiver is above 31.92dB, good SNR result for wireless communication. The optimization process by removing all hierarchical design has reduced the power and area consumption with 59.61% power saving and 30.07% area saving. MC-CDMA implementation on FPGA board gave a total of 28.57mW power consumption and used 2,072/114,480 logic elements which are 2% of overall logic elements. In conclusion, MC-CDMA receiver design in this thesis is small, low in power, have good SNR value and the ability to eliminate scheduling, which is suitable for WSN sensor nodes processor

DDoS detection using active and idle features of revised CICFlowMeter and statistical approaches

Distributed Denial of services (DDoS) attack is one of the most dangerous attacks that targeted servers. The main consequence of this attack is to prevent users from getting their legitimate services by bringing down targeted victim. CICFlowMeter tool generates bi-directional flows from packets. Each flow generates 83 of different features. The research focuses on 8 features which are active min (f1), active mean (f2), active max (f3), active std (f4), idle min (f5), idle mean (f6), idle max (f7), and idle std (f8). CICFlowMeter tool has several problems that affected on the detection accuracy of DDoS attacks. The idle and active based feature of Shannon entropy and sequential probability ratio test (SE-SPRT) approach was implemented in this research. The problems of original CICFlowMeter were presented, and the differences between original and revised version of CICFlowMeter tool were explored. The DARPA database and confusion matrix were used to evaluate the detection technique and present the comparison between two versions of CICFlowMeter. The detection method detected neptune and smurf attacks and had higher accuracy, f1-score, sensitivity, specificity, and precision when revised version of CICFlowMeter used to generate flows. However, the detection method failed to detect neptune attack and had higher miss-rate, lower accuracy, lower f1-score, and lower specificity, and lower precision when original version used in generating flows

Pipelined fast Fourier transform (FFT) processor power optimization

This paper presents the pipelined Fast Fourier Transform (FFT) processor power optimization. Pipelined FFT processor comprises of several sub-modules such as data buffer, shifter, and rotator (butterfly) which introduced power consumption to the circuit when in a hierarchical design. The objectives of this paper are, first, to study the power consumption in term of total dynamic power and cell leakage power during the hierarchical condition for different type of pipelined FFT and next, the objective is to study the power saving after the optimization process, where the design is flattened without sub-modules. This paper focuses on 16-point and 64-point pipelined FFT with radix-4 and radix-8 algorithms. The design process is in Verilog coding and simulation is in Modelsim Altera. Total dynamic power and cell leakage power for before and after the optimization process is performed using Synopsis. Overall, 16-point pipelined FFT with radix-4 algorithm has the best total dynamic power saving at 31.33% and 64-point pipelined FFT with radix-8 has the best cell leakage power saving with 58.83%. However, all pipelined FFT show lower power consumption after the optimization process. In conclusion, after the flattening process, power consumption reduced significantly