Planet Hunters. VIII. Characterization of 41 Long-Period Exoplanet Candidates from Kepler Archival Data

The census of exoplanets is incomplete for orbital distances larger than 1 AU. Here, we present 41 long-period planet candidates in 38 systems identified by Planet Hunters based on Kepler archival data (Q0-Q17). Among them, 17 exhibit only one transit, 14 have two visible transits and 10 have more than three visible transits. For planet candidates with only one visible transit, we estimate their orbital periods based on transit duration and host star properties. The majority of the planet candidates in this work (75%) have orbital periods that correspond to distances of 1-3 AU from their host stars. We conduct follow-up imaging and spectroscopic observations to validate and characterize planet host stars. In total, we obtain adaptive optics images for 33 stars to search for possible blending sources. Six stars have stellar companions within 4". We obtain high-resolution spectra for 6 stars to determine their physical properties. Stellar properties for other stars are obtained from the NASA Exoplanet Archive and the Kepler Stellar Catalog by Huber et al. (2014). We validate 7 planet candidates that have planet confidence over 0.997 (3-{\sigma} level). These validated planets include 3 single-transit planets (KIC-3558849b, KIC-5951458b, and KIC-8540376c), 3 planets with double transits (KIC-8540376b, KIC-9663113b, and KIC-10525077b), and 1 planet with 4 transits (KIC-5437945b). This work provides assessment regarding the existence of planets at wide separations and the associated false positive rate for transiting observation (17%-33%). More than half of the long-period planets with at least three transits in this paper exhibit transit timing variations up to 41 hours, which suggest additional components that dynamically interact with the transiting planet candidates. The nature of these components can be determined by follow-up radial velocity and transit observations.Comment: Published on ApJ, 815, 127 Notations of validated planets are changed in accordance with naming convention of NASA Exoplanet Archiv

Improvements towards Optimal Design of Reliable Subthreshold Digital CMOS with applications in Logic and Memory

This dissertation is organized as a collection of papers, where each paper represents original research contributions relating to the design and analysis of ultra low power CMOS, with a particular emphasis on ultra low voltage and subthreshold operation. The individual papers represent advancements particularily within methods and practices related to the design of both digital logic and memory circuits in the presence of severe process variation. At the device level it is demonstrated how the use of multiple minimum-width gates can exploit the inverse narrow-width subthreshold device effect to improve performance and power-delay products. Measurement results from a 90 nm prototype confirm the effect. Multi-objective optimization strategies are developed and applied to allow exploration of the Pareto optimal design space for reliable logic at 150mV. Targeting operation at 300mV, the design of a 9-transistor SRAM memory cell employing multi-Vt and virtual power techniques is presented. A multi-objective optimization strategy is developed and applied to achieve an optimal trade-off for an efficient and reliable sizing of the SRAM cell. Based on the 9-transistor cell, measured results from an ultra low voltage 64 × 32 SRAM module operating down to 273mV in a 65 nm technology indicate good yield and competitive performance metrics (17.8 fJ/access/bit at averages of 761 kHz @ 321mV supply). Finally, the behavior of subthreshold logic circuits under the influence of adverse fluctuations in the transistor threshold voltages is treated analytically, with specific emphasis on minimum-energy operation and yield constraints. The analysis can suggest optimal choices for supply voltage and device sizing, prior to simulation

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

Lütkemeier S, Jungeblut T, Berge HKO, Aunet S, Porrmann M, Rückert U. A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. IEEE Journal Of Solid-State Circuits. 2013;48(1):8-19.An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm(2) test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 sigma/mu), 567 fJ (0.037 sigma/mu), and 730 kHz (0.184 sigma/mu), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation