Means-end analysis of consumers’ perceptions of virtual world affordances for e-commerce

Virtual worlds are three-dimensional (3D) persistent multi-user online environments where users interact through avatars. The affordances of virtual worlds can be useful for business-to-consumer e-commerce. Moreover, affordances of virtual worlds can complement affordances of websites to provide consumers with an enhanced e-commerce experience. We investigated which affordances of virtual worlds can enhance consumers‟ experiences on e-commerce websites. We conducted laddering interviews with 30 virtual world consumers to understand their perceptions of virtual world affordances. A means-end analysis was then applied to the interview data. The results suggest co-presence, product discovery, 3D product experience, greater interactivity with products and sociability are some of the key virtual world affordances for consumers. We discuss theoretical implications of the research using dimensions from the Technology Acceptance Model. We also discuss practical implications, such as how virtual world affordances can be incorporated into the design of e-commerce websites

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment

Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

International audienceIn this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity (> 2 kΩ .cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 μm × 250 μm for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

International audienceThe recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results

CMOS pixel sensors on high resistive substrate for high-rate, high-radiation environments

In Press, Corrected Proof, Available online 4 February 2016 ;Please citethisarticleas:T.Hirono,etal.,NuclearInstruments&MethodsinPhysicsResearchA(2016), http://dx.doi.org/10.1016/j.nima.2016.01.088iInternational audienceA depleted CMOS active pixel sensor (DMAPS) has been developed on a substrate with high resistivity in a high voltage process. High radiation tolerance and high time resolution can be expected because of the charge collection by drift. A prototype of DMAPS was fabricated in a 150. nm process by LFoundry. Two variants of the pixel layout were tested, and the measured depletion depths of the variants are 166. μm and 80. μm. We report the results obtained with the prototype fabricated in this technology

Characterization of Fully Depleted CMOS Active Pixel Sensors on High Resistivity Substrates for Use in a High Radiation Environment

International audienceDepleted CMOS active sensors (DMAPS) are being developed for high-energy particle physics experiments in high radiation environments, such as in the ATLAS High Luminosity Large Hadron Collider (HL-LHC). Since charge collection by drift is mandatory for harsh radiation environment, the application of high bias voltage to high resistive sensor material is needed. In this work, a prototype of a DMAPS was fabricated in a 150nm CMOS process on a substrate with a resistivity of >2 k{\Omega}cm that was thinned to 100 {\mu}m. Full depletion occurs around 20V, which is far below the breakdown voltage of 110 V. A readout chip has been attached for fast triggered readout. Presented prototype also uses a concept of sub-pixel en/decoding three pixels of the prototype chip are readout by one pixel of the readout chip. Since radiation tolerance is one of the largest concerns in DMAPS, the CCPD_LF chip has been irradiated with X-rays and neutrons up to a total ionization dose of 50 Mrad and a fluence of 10E15neq/cm2, respectively