Selective Epitaxy of Group IV Materials for CMOS Application

As the International Technology Roadmap for Semiconductors (ITRS) demands an increase of transistor density in the chip, the size of transistors has been continuously shrunk. In this evolution of transistor structure, different strain engineering methods were introduced to induce strain in the channel region. One of the most effective methods is applying embedded SiGe as stressor material in source and drain (S/D) regions by using selective epitaxy. This chapter presents an overview of implementation, modeling, and pattern dependency of selective epitaxy for S/D application in CMOS. The focus is also on the wafer in and ex situ cleaning prior to epitaxy, integrity of gate, and selectivity mode

A generic coordination assembly-enabled nanocoating of individual tumor cells for personalized immunotherapy

A generic and effective tumor cells encapsulation strategy enabled by metal–organic coordination is developed to prepare a vaccine for personalized immunotherapy. Specifically, an epigallocatechin‐3‐gallate (EGCG)‐Al(III) coordination layer is in situ formed onto individual living cells in aqueous phase and the process can be completed within an hour. 98% of proteins in the cells are entrapped within the microparticles, which are endowed with high antigens loading capacity. The microparticles enhance the uptake efficiency of antigens, protect antigens from degradation in vivo, and delay the retention time of antigens in the lymph nodes. Moreover, dendritic cells (DCs) activation is triggered by the microparticles, and simultaneously, the expression of costimulation marker on DCs and the production of Th1‐related cytokines are significantly upregulated. Moreover, six kinds of tumor cells are utilized and successfully coated with the EGCG/Al(III) layer, suggesting the generalization of this strategy. More importantly, the microparticles exhibit a comparative antitumor effect with polyinosinic–polycytidylic acid (PolyI:C) in B16 pulmonary metastasis model. Overall, the encapsulation strategy enabled by metal–organic coordination can be potentially useful for personalized immunotherapy customized to individual patient's tumor cells

Undoped Strained Ge Quantum Well with Ultrahigh Mobility Grown by Reduce Pressure Chemical Vapor Deposition

We fabricate an undoped Ge quantum well under 30 nm Ge0.8Si0.2 shallow barrier with reverse grading technology. The under barrier is deposited by Ge0.8Si0.2 followed by Ge0.9Si0.1 so that the variation of Ge content forms a sharp interface which can suppress the threading dislocation density penetrating into undoped Ge quantum well. And the Ge0.8Si0.2 barrier introduces enough in-plane parallel strain -0.41% in the Ge quantum well. The heterostructure field-effect transistors with a shallow buried channel get a high two-dimensional hole gas (2DHG) mobility over 2E6 cm2/Vs at a low percolation density of 2.51 E-11 cm2. We also discover a tunable fractional quantum Hall effect at high densities and high magnetic fields. This approach defines strained germanium as providing the material basis for tuning the spin-orbit coupling strength for fast and coherent quantum computation.Comment: 11 pages, 5 figure

Special Issue: Silicon Nanodevices

In recent years, nanodevices have attracted a large amount of attention due to their low power consumption and fast operation in electronics and photonics, as well as their high sensitivity in sensor applications [...

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants

The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications

Si and SiGe Nanowire for Micro-Thermoelectric Generator : A Review of the Current State of the Art

In our environment, the large availability of wasted heat has motivated the search for methods to harvest heat. As a reliable way to supply energy, SiGe has been used for thermoelectric generators (TEGs) in space missions for decades. Recently, micro-thermoelectric generators (μTEG) have been shown to be a promising way to supply energy for the Internet of Things (IoT) by using daily waste heat. Combining the predominant CMOS compatibility with high electric conductivity and low thermal conductivity performance, Si nanowire and SiGe nanowire have been a candidate for μTEG. This review gives a comprehensive introduction of the Si, SiGe nanowires, and their possibility for μTEG. The basic thermoelectric principles, materials, structures, fabrication, measurements, and applications are discussed in depth.