24 research outputs found

    Níveis de lisina digestível em rações, em que se manteve ou não a relação aminoacídica, para frangos de corte de 1 a 21 dias de idade, mantidos em estresse por calor

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    Dois ensaios foram conduzidos para avaliar os efeitos de níveis de lisina digestível em rações em que se manteve ou não a relação aminoacídica sobre o desempenho de frangos de corte machos de 1 a 21 dias de idade, criados em alta temperatura. O delineamento experimental utilizado em ambos os ensaios foi o inteiramente casualizado. As aves, no ensaio 1, foram distribuídas em cinco tratamentos (0,92; 0,98; 1,04; 1,10 e 1,16% de lisina digestível em ração convencional), oito repetições e dez aves por repetição. No ensaio 2, os frangos foram distribuídos em quatro tratamentos (1,04; 1,10; 1,16 e 1,22% de lisina digestível em rações mantendo a relação aminoacídica), oito repetições e dez aves por repetição. No ensaio 1, os tratamentos influenciaram quadraticamente o ganho de peso e o consumo de ração, que aumentaram até os níveis de 1,14 e 1,09% de lisina, respectivamente. Embora a conversão alimentar tenha melhorado de forma linear, o modelo LRP foi o que melhor se ajustou aos dados, estimando em 1,097% o nível de lisina a partir do qual ocorreu um platô. Não houve efeito dos tratamentos sobre os pesos absolutos do coração, fígado e intestinos, enquanto o peso absoluto da moela aumentou linearmente. O peso absoluto da carcaça aumentou, enquanto os pesos relativos do coração e do fígado reduziram quadraticamente com os tratamentos. No ensaio 2, os tratamentos influenciaram de forma linear crescente o ganho de peso e a conversão alimentar, enquanto o consumo de ração não variou. Os tratamentos influenciaram linearmente o peso absoluto da carcaça, enquanto os pesos absoluto e relativo das vísceras não variaram. Concluiu-se que frangos de corte machos, de 1 a 21 dias de idade, mantidos em estresse por calor, exigem, no mínimo, 1,14 e 1,22% de lisina digestível em ração convencional e em ração em que se manteve a relação aminoacídica, respectivamente.Two trials were conducted to evaluate the effects of digestible lysine levels in diets maintaining or not the relationship of amino acids, on performance of broilers from 1 to 21 days, kept under heat stress. A completely randomized experimental design was used in both trials. In the trial 1, the broilers were allotted in five treatments (0.92; 0.98; 1.04; 1.10 and 1.16% of lysine in conventional diets), eight replicates and ten broilers per replicate. In the trial 2, the broilers were allotted in four treatments (1.04; 1.10; 1.16 and 1.22% of lysine in diet maintaining the relationship of amino acids), eight replicates and ten broilers per replicate. In the trial 1, the digestible lysine levels influenced quadraticly the weight gain and the feed intake that increased up to 1.14 and 1.09%, respectively. Although feed:gain ratio had changed by linear way, the LRP model adjusted better to the data, estimating in 1.097% the lysine level where occurred a "plateau". There was no effect of treatments on absolute weights of heart, liver and intestines, while the absolute weight of gizzard increased linearly. The absolute weight of carcass increased while the relative weights of heart and liver reduced quadraticly. In the trial 2, the treatments influenced in a crescent linear way the weight gain and the feed:gain ratio while the feed intake was not influenced. The treatments influenced linearly the absolute weight of carcass while the absolute and relative weights of the organs were not influenced. It was concluded that male broilers, in the period from 1 to 21 days of age, kept under heat stress, require at least 1.14 and 1.22% of digestible lysine in conventional diet and in diet maintaining the relationship of amino acid, respectively

    Herstellung von Multi-Gate-Strukturen zur Realisierung von elektrostatisch konfigurierbaren Bauelementen

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    In recent years, alternative concepts have been developed for field effect transistors, which allow further performance enhancement for large scale integrated circuits (ICs). One possibility is the production of so-called steep-slope transistors (SST). SSTs have a switching behavior with an inverse subthreshold slope SS less than 60 \,mV/dec, which is better than conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). A second way to increase performance is to make individual components more functional. This means, for example, that a future transistor can perform both n- and p-FET operations, as well as the aforementioned steep-slope applications. However, currently the functionality of a transistor is fixed by the profile of the dopants. To flexibly configure the potential landscape of a transistor, additional electrostatic gates are required along the direction of electronic transport through the device. In this thesis two concepts for the realization of electrostatically configurable devices are presented. The first considered device concept shows, in addition to the actual gate in the channel region, additional gates in in the source and drain region. These three gates form a tri-gate structure that will be used to control the potentials in ultra-thin silicon-on-insulator (SOI) layers and SOI nanowires (NWs). The second component concept considered in this work is based on a large number of buried, lateral gate structures, which are each separated by an insulator. These so-called multi-gate structures offer the possibility of implementing various configurations such as quantum dot systems, resonant tunnel diodes or even SSTs. For this, however, it is necessary, to scale down the gate lengths lGatel_\text{Gate} and distances between adjacent gates ldistancel_\text{distance} to lGate, distance<10l_\text{Gate, distance}<10\nm. Since the buried multi-gate structures are integrated into a Si substrate, a wide variety of semiconductor systems such as NWs, carbon nanotubes or even graphene can be applied to a multi-gate substrate and thus investigated in the simplest way. To further investigate the use of additional gates for the realization of SSTs and in particular TFETs, first simulations were performed to investigate the influence of geometrical and material-specific parameters on the performance and in particular the switching behavior of the TFETs. The simulation program for the calculation of the electrostatics and the current is based on the self-consistent solution of the Schroedinger and Poisson equation by means of the non-equilibrium Green Functions formalism. The work presents the different development processes needed for experimental implementation of the tri-and multi-gate structures. In addition, processes for structuring the SOI material are presented which was used as a channel material in the tri-gate structure. A combination of atomic layer deposition and inductively coupled plasma chemical vapor deposition was used to fabricate the multi-gate layer system. Therefore, the deposition processes within the scope of this work were analyzed in order to optimize the thin films necessary for the multi-gate structures regarding their electrical properties such as conductivity and insulation. The electrical characterization of the multi-gate layer system was carried out by current-voltage measurements. Since the gate structures are on the order of a few nanometers, a process had to be developed, which makes it possible to contact the individual layers by means of electron beam lithography. To demonstrate the functionality of the multi-gate structures as a device platform, vapor-liquid-solid grown InAs NWs were used. For this purpose, the InAs NWs were applied to the multi-gate substrates, and contacted with electron beam lithography and lift-off. The measurements on the InAs NW multi-gate transistors shown in the work, demonstrate the possibility of manipulating the electrical properties of the transistor through the individual gate electrodes

    Gate-Controlled Doping in Carbon-Based FETs

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    Buried multi-gate InAs-nanowire FETs

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    Hall effect measurements on InAs nanowires

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    We have processed Hall contacts on InAs nanowires grown by molecular beam epitaxy using an electron beam lithography process with an extremely high alignment accuracy. The carrier concentrations determined from the Hall effect measurements on these nanowires are lower by a factor of about 4 in comparison with those measured by the common field-effect technique. The results are used to evaluate quantitatively the charging effect of the interface and surface states

    Self-catalyzed VLS grown InAs nanowires with twinning superlattices

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    We report on the self-catalyzed growth of InAs nanowires by molecular beam epitaxy on GaAs substrates covered by a thin silicon oxide layer. Clear evidence is presented to demonstrate that, under our experimental conditions, the growth takes place by the vapor–liquid–solid (VLS) mechanism via an In droplet. The nanowire growth rate is controlled by the arsenic pressure while the diameter depends mainly on the In rate. The contact angle of the In droplet is smaller than that of the Ga droplet involved in the growth of GaAs nanowires, resulting in much lower growth rates. The crystal structure of the VLS grown InAs nanowires is zinc blende with regularly spaced rotational twins forming a twinning superlattice

    Gate-induced transition between metal-type and thermally activated transport in self-catalyzed MBE-grown InAs nanowires

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    Electronic transport properties of InAs nanowires are studied systematically. The nanowires are grown by molecular beam epitaxy on a SiOx-covered GaAs wafer, without using foreign catalyst particles. Room-temperature measurements revealed relatively high resistivity and low carrier concentration values, which correlate with the low background doping obtained by our growth method. Transport parameters, such as resistivity, mobility, and carrier concentration, show a relatively large spread that is attributed to variations in surface conditions. For some nanowires the conductivity has a metal-type dependence on temperature, i.e. decreasing with decreasing temperature, while other nanowires show the opposite temperature behavior, i.e. temperature-activated characteristics. An applied gate voltage in a field-effect transistor configuration can switch between the two types of behavior. The effect is explained by the presence of barriers formed by potential fluctuations
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