Efficient resources assignment schemes for clustered multithreaded processors

New feature sizes provide larger number of transistors per chip that architects could use in order to further exploit instruction level parallelism. However, these technologies bring also new challenges that complicate conventional monolithic processor designs. On the one hand, exploiting instruction level parallelism is leading us to diminishing returns and therefore exploiting other sources of parallelism like thread level parallelism is needed in order to keep raising performance with a reasonable hardware complexity. On the other hand, clustering architectures have been widely studied in order to reduce the inherent complexity of current monolithic processors. This paper studies the synergies and trade-offs between two concepts, clustering and simultaneous multithreading (SMT), in order to understand the reasons why conventional SMT resource assignment schemes are not so effective in clustered processors. These trade-offs are used to propose a novel resource assignment scheme that gets and average speed up of 17.6% versus Icount improving fairness in 24%.Peer ReviewedPostprint (published version

Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/

In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism for dynamically adapting the frequency and voltage of the frontend of the CMCD with the goal to optimize the energy-delay/sup 2/ product (ED2P). Our mechanism has minimal hardware cost, is entirely self-adjustable, does not depend on any thresholds, and achieves results close to optimal. We evaluate it on 16 SPEC 2000 applications and report 17.5% ED2P reduction on average (80% of the upper bound).Peer ReviewedPostprint (published version

Control speculation for energy-efficient next-generation superscalar processors

Conventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, increasing front-end energy and issue queue utilization and, thus, wasting around 30 percent of the power dissipated by a processor. Furthermore, processor design trends lead to increasing clock frequencies by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. As next-generation high-performance processors become deeply pipelined, the amount of wasted energy due to misspeculated instructions will go up. The aim of this work is to reduce the energy consumption of misspeculated instructions. We propose selective throttling, which triggers different power-aware techniques (fetch throttling, decode throttling, or disabling the selection logic) depending on the branch prediction confidence level. Results show that combining fetch-bandwidth reduction along with select-logic disabling provides the best performance in terms of overall energy reduction and energy-delay product improvement (14 percent and 10 percent, respectively, for a processor with a 22-stage pipeline and 16 percent and 13 percent, respectively, for a processor with a 42-stage pipeline).Peer ReviewedPostprint (published version

Virtual-physical registers

A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed all evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 19% increase in IPC for a machine with 64 physical registers in each file) when compared with the traditional register renaming approach.Peer ReviewedPostprint (published version

The change towards a teaching methodology based on competences: a case study in a Spanish university

The European Higher Education Area (EHEA) has promoted the implementation of a teaching methodology based on competences. Drawing on New Institutional Sociology, the present work aims to identify and improve knowledge concerning the factors which are hindering that change in the Spanish university system. This is investigated using a case study based on a Spanish university which is a pioneer in the implementation of a competence-based curriculum. The results show that factors identified and analysed are conditioning the change and causing a ceremonial adoption of the competence-based system by the teaching staff. The results of the study may be of use as a reference and orientation for educators and administrators as well as for the regulators of those countries integrated within the EHEA. The study may prove useful in the analysis of inertia factors present when designing and implementing the policies and measures necessary to achieve a comprehensive teaching methodology; one which incorporates learning and assessment of competences in a real manner

Reingeniería de Procesos de Negocio (BPR): Análisis de un caso desde la perspectiva del Nuevo Institucionalismo Sociológico

El BPR (Business Process Reengineering) se ha difundido recientemente entre las organizaciones para la implantación de los sistemas ERP (Enterprise Resource Planning). Este trabajo emplea el Nuevo Institucionalismo Sociológico y la Teoría de la Estructuración como enfoques teóricos complementarios para conocer mejor cómo pueden influir los entornos social y organizativo sobre la adopción del BPR para la implantación de un sistema ERP, así como las repercusiones que este cambio puede tener sobre las estructuras sociales a nivel de organización, prestando especial atención al papel desarrollado por los emprendedores institucionales. Para alcanzar este objetivo, hemos desarrollado un estudio de caso en un grupo multinacional de electricidad español que emprendió la reingeniería de sus procesos económico-financieros para la implantación de un sistema ERP. Los resultados del estudio evidencian la influencia de presiones tanto competitivas como institucionales sobre la organización para la adopción del BPR, así como los factores que motivaron a los actores dominantes a emprender un cambio radical. Asimismo, el estudio pone de manifiesto cómo el cambio analizado impactó sobre las estructuras sociales, pero también fue limitado por éstas

Migration and instabilities in institutionalized practices: a case study of a total quality management system in a Spanish electricity company

This paper presents empirical evidence on the attempts to migrate a Total Quality Management (TQM) practice of an acquired firm to the acquiring firm upon a takeover. The migration of the TQM was largely unsuccessful as it failed to achieve the same level of institutionalization it had in the acquired firm. Based on a longitudinal case study in two large Spanish electricity companies, the paper argues that the explanations for the failed migration lay in complex sets of political, functional and social factors, such as the deregulation of the Spanish electricity sector, the lost of the custodians or entrepreneurs of the TQM, and the normative fragmentation as a result of organizational restructuring undertaken by the acquiring firm. The paper contributes to calls for institutional theory researchers to extend their analysis to focus on instabilities and institutional change instead of the dominant view of stability and durability of institutionalized practices

Using MCD-DVS for dynamic thermal management performance improvement

With chip temperature being a major hurdle in microprocessor design, techniques to recover the performance loss due to thermal emergency mechanisms are crucial in order to sustain performance growth. Many techniques for power reduction in the past and some on thermal management more recently have contributed to alleviate this problem. Probably the most important thermal control technique is dynamic voltage and frequency scaling (DVS) which allows for almost cubic reduction in power with worst-case performance penalty only linear. So far, DVS techniques for temperature control have been studied at the chip level. Finer grain DVS is feasible if a globally-asynchronous locally-synchronous (GALS) design style is employed. GALS, also known as multiple-clock domain (MCD), allows for an independent voltage and frequency control for each one of the clock domains that are part of the chip. There are several studies on DVS for GALS that aim to improve energy and power efficiency but not temperature. This paper proposes and analyses the usage of DVS at the domain level to control temperature in a clustered MCD microarchitecture with the goal of improving the performance of applications that do not meet the thermal constraints imposed by the designers.Peer ReviewedPostprint (published version

Influences of institutional and relational contexts on adoption of total quality management: the case of Sevillana

La Gestión de la Calidad Total (TQM) ha sido adoptada por numerosas organizaciones en las dos últimas décadas. Desde la perspectiva del Nuevo Institucionalismo, Kostova y Roth (2002) identificaron varios patrones de adopción de las prácticas empresariales. Siguiendo este marco teórico, nos proponemos conocer cómo cambian los patrones de adopción de la TQM en las organizaciones en función de la variación de los componentes de sus entornos institucional y relacional. Para ello, hemos desarrollado un estudio de caso longitudinal en una compañía del sector eléctrico español que desde principios de los 90 se comprometió fuertemente con la TQM, siendo absorbida a mediados de esta década por el grupo empresarial líder del sector. Nuestros resultados ponen de manifiesto la influencia que tuvieron los componentes de los entornos de la organización estudiada y su evolución sobre el patrón de adopción de la TQM, así como la contribución de los isomorfismos mimético y normativo a la difusión de esta práctica empresarial entre las organizaciones del sector.Total Quality Management (TQM) has been adopted by many organizations in the last two decades. From the New Institutionalism perspective, Kostova and Roth (2002) identified several patterns of practice adoption. Following this theoretical approach, our aim is to understand the changes on patterns of TQM adoption in function of the variation of institutional and relational contexts. For it, we have conducted a longitudinal case study in a Spanish electricity company that was strongly engaged to TQM since the beginning of 90s. This company was acquired in the middle of 90s by the first business group of the Spanish electricity sector. Our results evidence the influence of the evolution of institutional and relational components on the pattern of TQM adoption of this organization. Also, our results show the contribution of the mimetic isomorphism and normative isomorphism to the diffusion of TQM among organizations of the industrial sector

Understanding the thermal implications of multicore architectures

Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level parallelism (TLP). In addition, it is a power and complexity-effective way of taking advantage of the huge number of transistors that can be integrated on a chip. On the other hand, today's higher than ever power densities have made temperature one of the main limitations of microprocessor evolution. Thermal management in multicore architectures is a fairly new area. Some works have addressed dynamic thermal management in bi/quad-core architectures. This work provides insight and explores different alternatives for thermal management in multicore architectures with 16 cores. Schemes employing both energy reduction and activity migration are explored and improvements for thread migration schemes are proposed.Peer ReviewedPostprint (published version