An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

In this work, we present the results of an investigation into charge trapping in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOS capacitors), which is analysed using the hysteresis exhibited in the capacitance-voltage (C-V) response. The availability of both n and p doped In0.53Ga0.47As epitaxial layers allows the investigation of both hole and electron trapping in the bulk of HfO2 and Al2O3 films formed using atomic layer deposition (ALD). The HfO2/In0.53Ga0.47As and Al2O3/In0.53Ga0.47As MOS capacitors exhibit an almost reversible trapping behaviour, where the density of trapped charge is of a similar level to high-k/In0.53Ga0.47As interface state density, for both electrons and holes in the HfO2 and Al2O3 films. The experimental results demonstrate that the magnitude of the C-V hysteresis increases significantly for samples which have a native oxide layer present between the In0.53Ga0.47As surface and the high-k oxide, suggesting that the charge trapping responsible for the C-V hysteresis is taking place primarily in the interfacial oxide transition layer between the In0.53Ga0.47As and the ALD deposited oxide. Analysis of samples with a range of oxide thickness values also demonstrates that the magnitude of the C-V hysteresis window increases linearly with the increasing oxide thickness, and the corresponding trapped charge density is not a function of the oxide thickness, providing further evidence that the charge trapping is predominantly localised as a line charge and taking place primarily in the interfacial oxide transition layer located between the In0.53Ga0.47As and the high-k oxide. (C) 2013 AIP Publishing LLC

Probing interface defects in top-gated MoS2 transistors with impedance spectroscopy

The electronic properties of the HfO2/MoS2 interface were investigated using multifrequency capacitance–voltage (C–V) and current–voltage characterization of top-gated MoS2 metal–oxide–semiconductor field effect transistors (MOSFETs). The analysis was performed on few layer (5–10) MoS2 MOSFETs fabricated using photolithographic patterning with 13 and 8 nm HfO2 gate oxide layers formed by atomic layer deposition after in-situ UV-O3 surface functionalization. The impedance response of the HfO2/MoS2 gate stack indicates the existence of specific defects at the interface, which exhibited either a frequency-dependent distortion similar to conventional Si MOSFETs with unpassivated silicon dangling bonds or a frequency dispersion over the entire voltage range corresponding to depletion of the HfO2/MoS2 surface, consistent with interface traps distributed over a range of energy levels. The interface defects density (Dit) was extracted from the C–V responses by the high–low frequency and the multiple-frequency extraction methods, where a Dit peak value of 1.2 × 1013 cm–2 eV–1 was extracted for a device (7-layer MoS2 and 13 nm HfO2) exhibiting a behavior approximating to a single trap response. The MoS2 MOSFET with 4-layer MoS2 and 8 nm HfO2 gave Dit values ranging from 2 × 1011 to 2 × 1013 cm–2 eV–1 across the energy range corresponding to depletion near the HfO2/MoS2 interface. The gate current was below 10–7 A/cm2 across the full bias sweep for both samples indicating continuous HfO2 films resulting from the combined UV ozone and HfO2 deposition process. The results demonstrated that impedance spectroscopy applied to relatively simple top-gated transistor test structures provides an approach to investigate electrically active defects at the HfO2/MoS2 interface and should be applicable to alternative TMD materials, surface treatments, and gate oxides as an interface defect metrology tool in the development of TMD-based MOSFETs

Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

We report on experimental observations of room temperature low frequency capacitance-voltage (CV) behaviour in metal oxide semiconductor (MOS) capacitors incorporating high dielectric constant (high-k) gate oxides, measured at ac signal frequencies (2 kHz to 1 MHz), where a low frequency response is not typically expected for Si or GaAs MOS devices. An analysis of the inversion regions of the CV characteristics as a function of area and ac signal frequency for both n and p doped Si and GaAs substrates indicates that the source of the low frequency CV response is an inversion of the semiconductor/high-k interface in the peripheral regions outside the area defined by the metal gate electrode, which is caused by charge in the high-k oxide and/or residual charge on the high-k oxide surface. This effect is reported for MOS capacitors incorporating either MgO or GdSiOx as the high-k layers on Si and also for Al2O3 layers on GaAs(111B). In the case of NiSi/MgO/Si structures, a low frequency CV response is observed on the p-type devices, but is absent in the n-type devices, consistent with positive charge (>8 x 10(10) cm(-2)) on the MgO oxide surface. In the case of the TiN/GdSiOx/Si structures, the peripheral inversion effect is observed for n-type devices, in this case confirmed by the absence of such effects on the p-type devices. Finally, for the case of Au/Ni/Al2O3/GaAs(111B) structures, a low-frequency CV response is observed for n-type devices only, indicating that negative charge (> 3 x 10(12) cm(-2)) on the surface or in the bulk of the oxide is responsible for the peripheral inversion effect. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4729331

Investigating positive oxide charge in the SiO2/3C-SiC MOS system

This paper investigates the origin of the fixed positive oxide charge often experimentally observed in Metal Oxide Semiconductor (MOS) structures of SiO2 formed on cubic silicon carbide (3C-SiC). The electrical properties of MOS structures including either thermally grown SiO2 or deposited SiO2 by Plasma Enhanced Chemical Vapour Deposition (PECVD) on epitaxial 3C-SiC layers grown directly on Si are investigated. MOS structures with a range of oxide thickness values subjected to different thermal treatments were studied. It was found that both thermally grown and deposited SiO2 on 3C-SiC exhibit similar positive charge levels indicating that the charge originates from interface states at the 3C-SiC surface and not from the oxide. The nature of this surface charge in the SiO2/3C-SiC system is also discussed based on the current data and previously published results