Towards low-dimensional hole systems in Be-doped GaAs nanowires

GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly-confined 0D and 1D hole systems with strong spin-orbit effects, motivating our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top-gates produced using GaAs nanowires with three different Be-doping densities and various AuBe contact processing recipes. We show that contact annealing only brings small improvements for the moderately-doped devices under conditions of lower anneal temperature and short anneal time. We only obtain good transistor performance for moderate doping, with conduction freezing out at low temperature for lowly-doped nanowires and inability to reach a clear off-state under gating for the highly-doped nanowires. Our best devices give on-state conductivity 95 nS, off-state conductivity 2 pS, on-off ratio ~$10^{4}$, and sub-threshold slope 50 mV/dec at T = 4 K. Lastly, we made a device featuring a moderately-doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance quantization highlighting the potential for future quantum device studies in this material system

Using ultra-thin parylene films as an organic gate insulator in nanowire field-effect transistors

We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we used to produce functional $\Omega$-gate and gate-all-around structures. These give sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding $10^3$ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically-treated nanowire surfaces; a feature generally not possible with oxides produced by atomic layer deposition due to the surface `self-cleaning' effect. Our results highlight the potential for parylene as an alternative ultra-thin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties

p-GaAs nanowire MESFETs with near-thermal limit gating

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio $\sim 10^{5}$, on-resistance ~700 k$\Omega$, contact resistance ~30 k$\Omega$, peak transconductance 1.2 $\mu$S/$\mu$m and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates whilst leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance

InAs nanowire transistors with multiple, independent wrap-gate segments

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favourable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.Comment: 18 pages, 5 figures, In press for Nano Letters (DOI below

Post-growth shaping and transport anisotropy in 2D InAs nanofins

We report on the post-growth shaping of free-standing 2D InAs nanofins that are grown by selective-area epitaxy and mechanically transferred to a separate substrate for device fabrication. We use a citric acid based wet etch that enables complex shapes, e.g., van der Pauw cloverleaf structures, with patterning resolution down to 150 nm as well as partial thinning of the nanofin to improve the gate response. We exploit the high sensitivity of the cloverleaf structures to transport anisotropy to address the fundamental question of whether there is a measurable transport anisotropy arising from wurtzite/zincblende polytypism in 2D InAs nanostructures. We demonstrate a mobility anisotropy of order 2-4 at room temperature arising from polytypic stacking faults in our nanofins. Our work highlights a key materials consideration for devices featuring self-assembled 2D III-V nanostructures using advanced epitaxy methods

Impact of invasive metal probes on Hall measurements in semiconductor nanostructures

Recent advances in bottom-up growth are giving rise to a range of new two-dimensional nanostructures. Hall effect measurements play an important role in their electrical characterization. However, size constraints can lead to device geometries that deviate significantly from the ideal of elongated Hall bars with currentless contacts. Many devices using these new materials have a low aspect ratio and feature metal Hall probes that overlap with the semiconductor channel. This can lead to a significant distortion of the current flow. We present experimental data from InAs 2D nanofin devices with different Hall probe geometries to study the influence of Hall probe length and width. We use finite-element simulations to further understand the implications of these aspects and expand their scope to contact resistance and sample aspect ratio. Our key finding is that invasive probes lead to significant underestimation of measured Hall voltage, typically of the order 40-80%. This in turn leads to a subsequent proportional overestimation of carrier concentration and an underestimation of mobility

P-GaAs Nanowire Metal-Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III–V complementary metal–oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal–semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal–GaAs interface. Our device beats the best-performing p-GaSb nanowire metal–oxide−semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on–off ratio ∼105, on-resistance ∼700 kΩ, contact resistance ∼30 kΩ, peak transconductance 1.2 μS/μm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.This work was funded by the Australian Research Council (ARC) grants DP170102552 and DP170104024, the University of New South Wales, Danish National Research Foundation, and the Innovation Fund Denmark

Regaining a Spatial Dimension: Mechanically Transferrable Two-Dimensional InAs Nanofins Grown by Selective Area Epitaxy

We report a method for growing rectangular InAs nanofins with deterministic length, width, and height by dielectrictemplated selective-area epitaxy. These freestanding nanofins can be transferred to lay flat on a separate substrate for device fabrication. A key goal was to regain a spatial dimension for device design compared to nanowires, while retaining the benefits of bottom-up epitaxial growth. The transferred nanofins were made into devices featuring multiple contacts for Hall effect and four-terminal resistance studies, as well as a global back-gate and nanoscale local top-gates for density control. Hall studies give a 3D electron density 2.5−5 × 1017 cm−3, corresponding to an approximate surface accumulation layer density 3−6 × 1012 cm−2 that agrees well with previous studies of InAs nanowires. We obtain Hall mobilities as high as 1200 cm2 /(V s), field-effect mobilities as high as 4400 cm2 /(V s), and clear quantum interference structure at temperatures as high as 20 K. Our devices show excellent prospects for fabrication into more complicated devices featuring multiple ohmic contacts, local gates, and possibly other functional elements, for example, patterned superconductor contacts, that may make them attractive options for future quantum information applications.This work was funded by the Australian Research Council (ARC) and the University of New South Wales