Du rétablissement de la vision binoculaire dans le traitement du strabisme

Thèse : Médecine : Université de Bordeaux : 1901N° d'ordre : 6

Les articles 212, SIS, 214 du code oivil. Examen critique de doctrine et de jurisprudence.

LEIDSSTELSELTh. Droit. Bordeaux.OPLADEN-RUG0

De la rédaction des formules de déclarations de successions et des pièces annexées / par G. Ginestous,...

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Les articles 212, 213, 214 du code civil, examen critique de doctrine et de jurisprudence : thèse pour le doctorat soutenue... / par Simone Ginestous,... ; Faculté de droit de l'Université de Bordeaux

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Electrical dispersion compensator for a giga-bit passive optical network system with Fabry-Perot laser

In this paper, we present an electrical dispersion compensator (EDC) for a 1.25 Gb/s Gigabit Passive Optical Network (GPON) with Fabry-Perot (FP) lasers. Due to modepartition noise (MPN) from the FP laser and fiber dispersion, GPON systems suffer from inter-symbol interference (ISI). The choice of the architecture for the EDC is a feed-forward equalizer (FFE) structure. The GPON experimental link was set-up with 0-15km fiber with a commercial triplexer. The EDC successfully compensates ISI for a given link with a 1.25 Gb/s PRBS signal. The EDC is implemented in 0.18 um CMOS technology with 54 mW power consumption from a 1.8 V power supply

An electronic dispersion compensator (EDC) with an analog eye-opening monitor (EOM) for 1.25-Gb/s gigabit passive optical network (GPON) upstream links

Today, network systems require higher bandwidth for applications such as fiber-to-the-home communications. Gigabit passive optical network (GPON) links using a Fabry-Perot laser are attractive solutions for this high-speed network. However, due to the mode partition noise and fiber dispersion, GPON systems suffer from inter-symbol interference (ISI). In this paper, we present an electronic dispersion compensator (EDC) that will improve a 1.25-Gb/s experimental GPON link. The experimental GPON link is simulated and measured with impairment assessment. An analog eye-opening monitor, which captures the quality of the EDC output signal using the tunable delay and the integrator is proposed. The proposed EDC successfully compensates ISI for a given link with a 1.25-Gb/s signal. All circuits are fabricated using a 0.18- $\mu{\hbox {m}}$ CMOS process.close3