Molecular breeding of Campanula for novel flower colour and ethylene insensitivity

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The Characterization and Classification Studies of Bent-onite Mines in IRAN for Application in Drilling and Foundry by AHP Technique

Bentonite is a clay groups which is a very important in todays industry, according to its chemical and physical properties. The most of the consumption of Bentonite in IRAN are in the fields of drilling and foundry. According to the drilling and foundry standards of IRAN, about 25 Bentonite mines have been identified and classified and lastly decided by AHP (Analytical Hierarchy Process) technique. More than 300 tests about the parameters like wetness, swelling, compressive strength, dry strength, pH, methylen blue, gelling index, yield, viscosity, plastic viscosity, filter loss and sieve analysis have been investigated. The Tashtabkhor mine with highest score (19.85) and the Chahkeshmir mine with lowest score (4.523) in drilling and the Boteh gaz mine with highest score (19.37) and the Gol khandan mine with lowest score (5.094)in foundry, were the mines selected amount 25 mines

Energy-Efficient Approximate Least Squares Accelerator:A Case Study of Radio Astronomy Calibration Processing

Approximate computing allows the introduction of inaccuracy in the computation for cost savings, such as energy consumption, chip-area, and latency. Targeting energy efficiency, approximate designs for multipliers, adders, and multiply-accumulate (MAC) have been extensively investigated in the past decade. However, accelerator designs for relatively bigger architectures have been of less attention yet. The Least Squares (LS) algorithm is widely used in digital signal processing applications, e.g., image reconstruction. This work proposes a novel LS accelerator design based on a heterogeneous architecture, where the heterogeneity is introduced using accurate and approximate processing cores. We have considered a case study of radio astronomy calibration processing that employs a complex-input iterative LS algorithm. Our proposed methodology exploits the intrinsic error-resilience of the aforesaid algorithm, where initial iterations are processed on approximate modules while the later ones on accurate modules. Our energy-quality experiments have shown up to 24% of energy savings as compared to an accurate (optimized) counterpart for biased designs and up to 29% energy savings when unbiasing is introduced. The proposed LS accelerator design does not increase the number of iterations and provides sufficient precision to converge to an acceptable solution

Propagation of Delay in Probabilistic CMOS Systems

Future low voltage noise dominated designs render probabilistic behavior of CMOS. This is acceptable as far as applications’ intrinsic error resilience allows quantified inaccuracy in results to save energy consumption, such as in applications like audio/video processing and sky image formation in radio astronomy. This introduces the trade-off between energy consumption (E) and probability of correctness (p) that provides an opportunity for inexact computing to attain higher energy efficiency. Efforts have been made in the last decade to model probabilistic CMOS (PCMOS) keeping in view the noise variance and to establish its feasibility for error resilient applications focused on the nominal voltage range. However, exploiting the near threshold voltage (NTV) range is quite a promising energy efficient design technique that operates the hardware at relatively slower pace while retaining the deterministic property of computations. We propose to take the advantage of energy efficiency at NTV while retaining the speed as constant, sacrificing p to the extent allowed by applications resilience. In this regard, we investigated the impact of NTV operation on PCMOS where more energy can be saved with less accurate results. Our simulation results of an inverter and a 4-bit ripple carry adder in Cadence showed the shortcomings of current analytical models for probability of correctness at NTV and lower voltage supplies. We further investigated the impact of delay propagation in a digital system composed of probabilistic building blocks, which provides a clear insight of timing delay affecting the higher significant computational bits more than its lower significant counterparts and hence contributing considerably to the total error

Non-binary compound codes based on single parity-check codes.

Thesis (Ph.D.)-University of KwaZulu-Natal, Durban, 2013.Shannon showed that the codes with random-like codeword weight distribution are capable of approaching the channel capacity. However, the random-like property can be achieved only in codes with long-length codewords. On the other hand, the decoding complexity for a random-like codeword increases exponentially with its length. Therefore, code designers are combining shorter and simpler codes in a pseudorandom manner to form longer and more powerful codewords. In this research, a method for designing non-binary compound codes with moderate to high coding rate is proposed. Based on this method, non-binary single parity-check (SPC) codes are considered as component codes and different iterative decoding algorithms for decoding the constructed compound codes are proposed. The soft-input soft-output component decoders, which are employed for the iterative decoding algorithms, are constructed from optimal and sub-optimal a posteriori probability (APP) decoders. However, for non-binary codes, implementing an optimal APP decoder requires a large amount of memory. In order to reduce the memory requirement of the APP decoding algorithm, in the first part of this research, a modified form of the APP decoding algorithm is presented. The amount of memory requirement of this proposed algorithm is significantly less than that of the standard APP decoder. Therefore, the proposed algorithm becomes more practical for decoding non-binary block codes. The compound codes that are proposed in this research are constructed from combination of non-binary SPC codes. Therefore, as part of this research, the construction and decoding of the non-binary SPC codes, when SPC codes are defined over a finite ring of order q, are presented. The concept of finite rings is more general and it thus includes non-binary SPC codes defined over finite fields. Thereafter, based on production of non-binary SPC codes, a class of non-binary compound codes is proposed that is efficient for controlling both random-error and burst-error patterns and can be used for applications where high coding rate schemes are required. Simulation results show that the performance of the proposed codes is good. Furthermore, the performance of the compound code improves over larger rings. The analytical performance bounds and the minimum distance properties of these product codes are studied

Analysis of Residual Stresses in Thermoplastic Composites Manufactured by Automated Fiber Placement

Process-induced stresses can play a major role in degradation of a part or structure made of composite materials. The new Automated Fiber Placement (AFP) manufacturing method of composites allows manufacturers and designers to potentially manufacture composite parts with greater precision and speed. However, for the case of thermoplastic composites because of extreme manufacturing environment such as high temperature these advantages could be jeopardized by process-induced residual stresses. In this work we looked into process-induced stresses caused by interaction of mold and composites considering temperature dependency and time dependency behavior of composite materials and proposed a new numerical step-by-step scheme to take into account mechanisms of stress generation and stress relaxation. Also, an in situ strain measurement using Digital Image Correlation (DIC) is proposed to measure strains of the composite tape during manufacturing