Observation of the stacking faults in In0.53Ga0.47As by electron channeling contrast imaging

The observation and interpretation of Frank stacking faults, Shockley stacking faults, Lomer dislocations, and 60 degrees misfit dislocations, which have similar line shapes in the (001) In0.53Ga0.47As crystalline surface, are performed with the electron channeling contrast imaging (ECCI) technique. To minimize the backscattered electron (BSE) contrast that resulted from the surface morphology, a relatively flat region is first selected and compared with an atomic force microscopy (AFM) image and then, subsequently, examining ECCI with transmission electron microscopy (TEM)-like invisibility criteria. By orthogonally choosing the diffraction vector g between (220) and (2-20), misfit dislocations seem to be always visible but partially faint in the g parallel to the line direction on the surface. With respect to the image contrast, Frank stacking faults and Lomer dislocations are likely to be completely invisible for parallel g. The criteria are further confirmed by cross-sectional TEM analysis, which shows a preferred homogeneous surface nucleation

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

peer reviewedWe report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform

Lifetime Assessment of In(x)Ga(1-x)As n-Type Hetero-Epitaxial Layers

Herein, the carrier lifetime in approximately 5x10^16 cm^(-3) n-doped In(x)Ga(1-x)As layers is studied by diode current–voltage analysis and by time-resolved photoluminescence. Two sets of hetero-epitaxial layers are grown on semi-insulating InP or GaAs substrates. The first set corresponds with a constant In content p + n stack, while the second set has a fixed x = 0.53 for the n-layer, while containing various extended defect densities by using a strain relaxed buffer with different x. This results in threading dislocation densities (TDDs) between approximately 10^5 cm^(-2) and a few 10^9 cm^(-2). It is shown that the overall trend of the recombination lifetime versus TDD can be described by a first-order model considering a finite recombination lifetime value inside a dislocation core of 1 nm. For the generation lifetime, a strong electric-field enhancement factor is found. Also, the residual strain in the n-layer has an impact. Overall, the safe limit for TDD depends on the type of application and on the operation conditions (reverse diode bias)

(Invited) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling

International audienceWe report on vertically stacked nanosheet (NS) FET devices as the most promising candidates to replace finFETs, discussing some of their key features and potential extension and/or alternative options to help preserve the power, performance, area, and cost (PPAC) logic roadmap for advanced sub-5nm technology nodes, being also attractive for cold computing. In addition, given the increased complexity and cost in back-end-of-line processing, to take full advantage of the scaling performance benefits at transistor level it has also become ever more pressing to address signal and power wiring bottlenecks. The concept of moving power delivery to the wafer’s backside has been gaining traction and we will thus also explore it in this work by combining logic and 3D technologies and assess its feasibility by evaluating the impact of 3D processing on device characteristics

Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach

The research into alternative channel materials to improve CMOS performance is a rapidly growing area of research. III–V and Ge based MOSFETs offer attractive possibilities for a high performance and low power circuit implementation. Here, we report a global performance analysis of future DualLogic CMOS based on the new, Implant-FreeQuantum-Well device architecture for both III–V nMOSFETs and Ge pMOSFETs. The III–V nMOSFETs are optimised to achieve low leakage, high performance and its performance is evaluated using ensemble Monte Carlo simulations. A similar approach is adopted for the Ge pMOSFETs. In addition, the impact of the interface states density on the output characteristics is also studied. Finally, the timing performance of the DualLogic CMOS is evaluated using mixed mode TCAD and circuit simulations

Defect assessment and leakage control in Ge junctions

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Prediction of the influence of induced stresses in silicon on CMOS Performance in a Cu-through-via interconnect technology

One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to attach them to a next level die by means of thermocompression bonding. This results in induced stresses in the silicon due to the large CTE disparity between copper and silicon, and also from the force applied during thermocompression bonding. These stresses can have an impact on the performance of the transistors and may as well result in die fracture. This paper studies these stresses through Finite Element modeling. We found that the keep-away-zone of the transistors from the copper via where transistor performance is impacted by the through-Si interconnect proximity, is proportional to the via diameter. The bonding temperature is found to be the main cause for the induced stresses during the thermo-compression bonding process. The induced stresses in silicon decrease with decreasing the silicon thickness.status: publishe

Observation of the Stacking Faults in In0.53Ga0.47As by Electron Channeling Contrast Imaging

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The impact of extended defects on the generation and recombination lifetime in n type In.Ga-53.As-47

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Bandlike and localized states of extended defects in n-type In0.53Ga0.47As

© 2018 Author(s). In0.53Ga0.47As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In0.53Ga0.47As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum EC is assigned to the "localized" states of α 60° misfit dislocations; another broad electron trap with mean activation energies between EC- 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor KT by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at EV+ 0.42 ± 0.01 and EV+ 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (VGa/In3-/2-) and 60° β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects AsGa/In are discussed for n-type In0.53Ga0.47As.status: publishe