An Original SiGe Active Differential Output Power Splitter for Millimetre-wave Applications

This paper deals with an original design of an active power splitter featuring a differential output presenting a greatly enhanced even mode rejection.The proposed circuit consists in two cascaded common emitter and common collector differential pairs.For achieving the best performance,it is shown that each of these two differential pairs requires a specific common node to ground impedance that is discussed.The circuit has been implemented on a 0.25 µm SiGe BiCMOS process and exhibits anticipated phase and amplitude broadband unbalance less than 6.5 ° and 0.6 dB respectively all over the 6 -27 GHz frequency range.At 20 GHz,a common mode rejection ratio better than 43 dB is predicted,i.e.a maximum 0.12 dB /0.35 ° output signal unbalance

Ka-band Coplanar Low-Noise Amplifier Design with Power PHEMTs

The design of a coplanar low-noise amplifier (LNA)is presented in this paper.Pseudomorphic high electron mobility transistors (PHEMTs),optimized for power applications,are used in order to evaluate the potentiality of this technology for mixed-mode applications. The three stages amplifier noise figure is lower than 2.6 dB on the 27 -31 GHz frequency band with a 20 dB power gain

Bruit en 1/f3/2 dans les structures GaAs. Modèle du bruit thermique de surface

Cet article présente divers résultats expérimentaux concernant le bruit en 1/f3/2 de différentes structures GaAs. L'analyse des résultats semble mettre en défaut l'hypothèse d'un bruit de diffusion d'ions généralement évoquée pour expliquer l'origine du bruit en 1/f 3/2. Nous développons un nouveau modèle de « Bruit Thermique de Surface » basé sur l'existence de générateurs de bruit thermique distribués tout au long de l'interface semiconducteur-air des composants

Low Frequency Noise Deviation from Schottky theory in p-n junctions

International audienceTheories on linear white noise sources such as thermal noise or shot noise are well established and massively used for low noise device modeling and circuit design. However, it has been experienced that diffusion noise in a large variety of pn diodes (transistors) can deviate from the expected value given by the Schottky theorem or by the Van der Ziel representation commonly used. In this work, more than ten types of pn junctions have been investigated, all featuring an increase of the diffusion noise floor in the low frequency band when operated under low d.c current conditions. These specific conditions certainly explain why such phenomenon has not been reported earlier; however, this noise degradation becomes a problem as many systems make use of pn diodes for low signal photodetection (PPD or CCD), operating at very low (dark) current. For the first time, we report current spectral densities deviations from the Shottky theorem at low frequency; a focus on the experimental workbench is given to remove any doubt regarding the opportunity to analyze data under concern. Then, low frequency noise spectra are presented for various diodes and pn junctions, and a model is proposed. Impedance spectroscopy is also used to support this study. Keywords-Low frequency noise, diffusion noise, noise frequency dispersion

Optimisation du profil de dopage d'un MESFET réalisé par implantation ionique

On analyse l'interdépendance entre les performances d'un transistor à effet de champ en arséniure de gallium et son profil de dopage réalisé par implantation ionique. On étudie en particulier l'influence des conditions d'implantation (énergie et dose implantées) ainsi que celle du creusement de grille (« recess ») préalablement à la réalisation de la barrière Schottky. Les résùltats théoriques ont été obtenus à l'aide d'un simulateur permettant d'accéder aux propriétés statiques et dynamiques petits signaux du transistor à effet de champ pour tout profil de dopage non uniforme. Le temps de calcul a été réduit au maximum en associant des techniques analytiques et numériques. Le fonctionnement général du logiciel ainsi que les principes du calcul de toutes les caractéristiques électriques du composant sont détaillés. Les résultats de la simulation sont comparés aux résultats expérimentaux obtenus sur des structures réalisées en faisant varier les conditions d'implantation et la profondeur du creusement de grille. Enfin, l'influence du profil de dopage sur chacun des éléments du schéma équivalent du transistor à effet de champ GaAs est discutée en vue d'une optimisation des performances micro-ondes

Le transistor à effet de champ à grille Schottky au GaAs : analyse et modèle mathématique du fonctionnement avec la grille en polarisation directe

Dans cet article, une analyse théorique et expérimentale, en régime statique, du comportement du transistor à effet de champ à l'arséniure de gallium à grille Schottky, lorsque la grille est en polarisation directe, est présentée. Dans la première partie, où la grille est considérée comme un schéma distribué suivant la direction transversale Z, une expression analytique de la résistance équivalente de la métallisation de grille, statique ou dynamique, est proposée et permet de définir dans quelles conditions l'approximation classique R/3 est valable, R étant la résistance de métallisation de grille. Dans la deuxième partie, un modèle mathématique du transistor, lorsque la grille est distribuée suivant la longueur L de grille, est établi et permet de simuler les caractéristiques électriques ID(VD, VG) et IG(VD, VG) lors du fonctionnement avec la grille en polarisation directe

Impact of the Frequency Dependence of the Parasitic Admittance on the Diffusion Noise of a Diode Junction at Low Bias

International audienceIn this article, we report for the first time that the well-established diffusion noise can be apparently increased in large proportions and that such a situation can be very common at some specific frequencies in the p-n junction structures operating at a very low direct bias current. Noise theories and the associated measurement techniques are a major issue for the emerging semiconductor technologies, the development of accurate computer-aided design (CAD) models, and the designing of low-noise circuits and systems. The conventional shot noise model usually satisfactorily describes the p-n junction noise in solid-state devices, such as diodes and transistors. It has proven to be very efficient for many different conventional and advanced semiconductor technologies. However, alterations may sometimes be needed as previous works indicate scenarios where this so-called shot noise exhibits deviations from the theory, which translates into some noise suppression. In this article, we report on alterations that look like low-frequency diffusion noise enhancement (unexpected noise increase). It occurs at low current levels , for many generic commercially available diodes and the p-n junctions in transistors. Therefore, we propose an appropriate electrical noise model that satisfies both the low-frequency noise experimental data and the electrical behavior of the devices observed from impedance spec-troscopy. We also evaluate this model as the ambient temperature is varied. Finally, it is discussed how this model can be connected to the conventional van der Ziel shot noise model and a better insight on the possible origin of such diffusion noise enhancement is provided

Conception réalisation et caractérisation de structures micro-usinées sur silicium (applications aux micro-systèmes millimétriques)

TOULOUSE3-BU Sciences (315552104) / SudocSudocFranceF

Secured Failure Analysis Methodology for Accurate Diagnostic of Defects in GaN HEMT Technologies

International audienceIII-V wide bandgap disruptive technology is positioned as a leader for high power segments operating at high frequency or under switching mode. Still, it is needed to investigate these transistors to push the maturity towards higher levels and to address elevated junction temperatures. Concerning analog RF applications, more than two decades of studies lay the main technological process basis. However, if failure signatures and their associated defects are now issues likely to be understood as individual problems, the global failure behavior in active high frequency analog devices still poses challenges to overcome. This paper is a contribution to the failure analysis studies on GaN technologies by providing a methodology for ensuring the validity of the stress analysis; this procedure is suitable even for a single stress test campaign, when usually several accelerated life tests are needed to separate concurrently proceeding effects. This methodology is based on the use of non-destructive and eventually destructive characterization techniques, as well as electrical TCAD modelling

Methodology for accurate diagnostic of defects in III-N HEMT technologiesNon-destructive and destructive experimental tools-electrical and T-CAD models

International audienceIII-V wide bandgap disruptive technology is firmly positioned as a leader for high power segments operating at high frequency or under switching mode. Still, it is needed to investigate these transistors to push the maturity towards higher levels and to address elevated junction temperatures. Concerning analog RF applications, more than two decades of studies lay the main technological process basis for both obtaining improved RF performances and reliability. However, if failure signatures and their associated defects are now issues likely to be understood as individual problems, the global failure behavior still poses challenges to overcome. This paper is a contribution to the failure analysis studies on GaN technologies by providing a methodology for ensuring the validity of the stress analysis, to the accurate identification of the involved defects; this procedure is suitable even for a single stress test campaign, when usually several accelerated life tests are needed to separate concurrently proceeding effects. This methodology is based on the use of destructive and non-destructive characterization techniques, as well as electrical modelling. Key degradation processes are highlighted from different feedback studies, still considering the need of a secure procedure to avoid any misunderstanding about the origin of the tracked DC or RF variation of the devices under test