A Methodology to Account for the Finger Non-Uniformity in Photovoltaic Solar Cell

Abstract In this work we investigate the impact of a non-uniform finger in the front-side metallization on the performance of c-Si solar cells. For this purpose, we propose a methodology based on a mixed-mode simulation approach, which allows evaluating the solar cell properties by performing both numerical device simulations and circuit simulations. The finger roughness profile is modeled by means of Gaussian function. The impact of roughness on the solar cell efficiency is studied as a function of mean finger height, mean finger width and finger resistivity. The proposed methodology has been applied to typical roughness profiles realized with two different metallization techniques, the conventional single screen-printing (SP) and the double screen-printing (DP)

Nanofocused X-ray beam to reprogram secure circuits

International audienceSynchrotron X-ray nano-beamlines is investigated as a tool to perturb microcontroller circuits. This technique is used to target the Flash, EEPROM and RAM memory of a circuit. The obtained results are very promising and show that it is possible to corrupt a single transistor in a semi-permanent state. A simple heat treatment can remove the induce effect, thus making the corruption reversible. A concrete attack on a code stored in Flash is demonstrated

Forming Gas Anneal effect on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step

Correlation Between Soft Breakdown and Plasma Process Induced Damage

The correlations between soft breakdown (SB) and plasma process induced damage of devices with ultra-thin gate oxides were presented. A stress and test methodology was proposed to analyze SB due to sudden decrease in gate voltage during a constant current stress. The voltage used for measurements was kept small to avoid Fowler-Nordheim tunneling. The analysis suggested the dependence of cummulative failure distribution on antenna ratio. It was found that the use of low voltages caused more localized damage and increased the chance trigger SB spot into conduction

Radiation Induced Charge Loss Mechanisms Across the Dielectrics of Floating Gate Flash Memories

One of the key factors permitting the extraordinary success offloating gate (FG) nonvolatile memories relies on the excellentinsulating properties of the dielectric layers surrounding theFG itself. Among other threats, ionizing radiation mayeffectively affect such insulating characteristics, leading to adegradation of the FG stored charge. Radiation effects have beentraditionally studied for niche applications such as the highenergy physics or the satellite industry. However, modernsemiconductor technologies are becoming more and more sensitiveto the deposition of small amounts of charge, such as thosegenerated by the byproducts of atmospheric neutrons, and FGmemories are in fact aggressively scaled following Moore's lawpredictions. Loss of information may derive from two broadcategories of phenomena, Total Ionizing Dose and Single EventEffect, whose actions on the FG dielectrics are reviewed in thiscontribution from the viewpoints of the prompt induced damageand long-term degradation effects, affecting the memoryretention capabilities

Plasma-induced Micro Breakdown in small area MOSFETs

Plasma treatments, indispensable for manufacturing of ULSI integrated circuits, may lead to a latent damage in gate oxides of CMOS components. Latent damage may endanger the device long-term reliability, which is usually tested over large area MOS devices. In this work, we investigated the impact of latent plasma induced damage on the reliability of nMOSFETs with small gate area and gate oxide thickness of 3.2 nm. To this purpose, we stressed 1,500 devices with different antenna areas by using a staircase-like stress voltage, and by monitoring the gate leakage at the gate voltage VG=2V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current is characterized by two different oxide breakdown modes. The first is the well-known HardBreakdown, while the second one, which we called Micro Breakdown, can be modeled as a Double Trap Assisted Tunneling mechanism, and is characterized by a very small leakage current (around 100pA at the gate voltage VG=2V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of micro broken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). For converse, the Hard Breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linkedto the different generation mechanisms involved in Micro Breakdown and Hard Breakdown phenomena