Fast multichannel analog storage system

A Multichannel Analog Storage System based on a commercial 32-channel parallel in/serial out (PISO) analog shift register is described. The basic unit is a single width CAMAC module containing 512 analog cells and the associated logic for data storage and subsequent readout. At sampling rates of up to 30 MHz the signals are strobed directly into the PISO. At higher rates signals are strobed into a fast presampling stage and subsequently transferred in block form into an array of PISO's. Sampling rates of 300 MHz have been achieved with the present device and 1000 MHz are possible with improved signal drivers. The system is well suited for simultaneous handling of many signal channels with moderate numbers of samples in each channel. RMS noise over full scale signal has been measured as 1:3000 (approx. = 11 bit). However, nonlinearities in the response and differences in sensitivity of the analog cells require an elaborate calibration system in order to realize 11 bit accuracy for the analog information

Performance report for Stanford/SLAC Microstore Analog Memory Unit

Tests of a newly developed Analog Memory Unit (AMU) are described. The device contains 256 analog storage cells consisting of pass transistors, a storage capacitor and a differential read out buffer. By addressing the storage cells sequentially, the shape of the signal present at the input can be recorded in time. Fast response and good amplitude resolution were the design goals for the development. Measurements on individual devices will be presented and the status of hybridized subsystems containing eight AMUs discussed

Waveform Sampler CAMAC Module

A Waveform Sampler Module (WSM) for the measurement of signal shapes coming from the multi-hit drift chambers of the SLAC SLC detector is described. The module uses a high speed, high resolution analog storage device (AMU) developed in collaboration between SLAC and Stanford University. The AMU devices together with high speed TTL clocking circuitry are packaged in a hybrid which is also suitable for mounting on the detector. The module is in CAMAC format and provides eight signal channels, each recording signal amplitude versus time in 512 cells at a sampling rate of up to 360 MHz. Data are digitized by a 12-bit ADC with a 1 ..mu..s conversion time and stored in an on-board memory accessible through CAMAC

(1) DESIGN AND FABRICATION OF ADVANCED HYBRID CIRCUITS FOR HIGH ENERGY PHYSICS’

Current design and fabrication techniques of hybrid devices are explained for the Drift Chamber and the Liquid Arpon Calorimeter for the Stanford Linear Collider Large Detector (SLD) at SLAC. Methods of developing layouts, raging from hand-cut templates to advanced designs utilizing CAD tools with special hybrid design software were applied. Physical and electrical design rules for good yield and performance are discussed. Fabrication and assembly of the SLD hybrids are described. 1

The front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector

The front-end signal processing electronics for the drift-chambers of the Stanford Large Detector (SLD) at the Stanford Linear Collider is described. The system is implemented with printed-circuit boards which are shaped for direct mounting on the detector. Typically, a motherboard comprises 64 channels of transimpedance amplification and analog waveform sampling, A/D conversion, and associated control and readout circuitry. The loaded motherboard thus forms a processor which records low-level wave forms from 64 detector channels and transforms the information into a 64 k-byte serial data stream. In addition, the package performs calibration functions, measures leakage currents on the wires, and generates wire hit patterns for triggering purposes. The construction and operation of the electronic circuits utilizing monolithic, hybridized, and programmable components are discussed