Performance and robustness characterisation of SiC power MOSFETs

Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics

Static and dynamic TSEPs of SiC and GaN transistors

This paper investigates the static and dynamic temperature sensitive electrical parameters (TSEPs) for both SiC and GaN transistors. It is shown that both the qualitative and quantitative temperature characteristics of these parameters are various when different type of transistors are concerned. This finding can be used to select the most appropriate temperature sensitive parameter for the device under specific situation. In this paper, two types of transistors, SiC SCT2080KE MOSFET and GaN PGA26E19BA HEMT are evaluated and compared in terms of six TSEPs, including source-drain reverse bias voltage (VSD), static on-resistance (RDS,ON), gate threshold voltage (VGS(TH)), transconductance (gm), dIDS/dt switching transients and gate current (IG). Then, these TSEPs are compared using four criteria: temperature sensitivity, linearity, material and the capability of on-line temperature monitorin

Performance and robustness characterisation of SiC power MOSFETs

Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics

A New Form of Interlocking Developing Technology for Level Crossings and Depots with International Applications

There are multiple large rail infrastructure projects planned or currently being undertaken within the United Kingdom. Many of these projects aim to reduce the continual issue of limited or overcapacity service. These projects involve an expansion of Rail lines, introducing faster lines, improved stations in towns and cities and better communication networks. Some major projects like Control Period 6 (CP6) are being managed by Network Rail; where projects are initiated throughout Great Britain. Many projects are managed outside Great Britain e.g., Trans-European Transport Network Program, which is planning for expansion of Rail lines (almost double) for High-Speed Rails (category I and II). These projects will increase the number of junctions and Level Crossings. A Level Crossing is where a Rail Line is crossed by a road or a walkway without the use of a tunnel or bridge. The misuse from the road users account for nearly 90% of the fatalities and near misses at Level Crossings. During 2016/2017, the Rail Network recorded 6 fatalities, about 400 near-misses and more than 77 incidents of shock and trauma. Accidents at Level Crossings represent 8% of the total accidents from the whole Rail Network. Office of Rail and Road (ORR) suggested that among these accidents at Level Crossings 90% of them are pedestrians. Such high numbers of accidents, fatalities and high risk have alarmed authorities. These authorities found it necessary to invest time and utilise given resources to improve the safety system at a Level Crossing using the safer and reliable interlocking system. The interlocking system is a feature of a control system that makes the state of two functions mutually independent. The primary function of Interlocking is to ensure that trains are safe from collision and derailment. Considering the risk associated with the Level Crossing system, the new proposed interlocking system should utilise the sensing system available at a Level Crossing to significantly reduce implementation cost and comply with the given standards and Risk Assessments. The new proposed interlocking system is designed to meet the “Safety Integrity Level- SIL” and possibly use the “2oo2” approach for its application at a Level Crossing, where the operational cycle is automated or train driver is alarmed for risk situations. Importantly, the new proposed system should detect and classify small objects and provide a reasonable solution to the current risk associated with Level Crossing, which was impossible with the traditional sensing systems. The present work discusses the sensors and algorithms used and has the potential to detect and classify objects within a Level Crossing area. The review of existing solutions e.g Inductive Loops and other major sensors allows the reader to understand why RADAR and Video Cameras are preferable choices of a sensing system for a Level Crossing. Video data provides sufficient information for the proposed algorithm to detect and classify objects at Level Crossings without the need of a manual “operator”. The RADAR sensing system can provide information using micro-Doppler signatures, which are generated from small regular movements of an obstacle. The two sensors will make the system a two-layer resilient system. The processed information from these two sensing systems is used as the “2oo2” logic system for Interlocking for automating the operational cycle or alarm the train drive using effective communication e.g., GSM-R. These two sensors provide sufficient information for the proposed algorithm, which will allow the system to automatically make an “intelligent decision” and proceed with a safe Level Crossing operational cycle. Many existing traditional algorithms depend on pixels values, which are compared with background pixels. This approach cannot detect complex textures, adapt to a dynamic background or avoid detection of unnecessary harmless objects. To avoid these problems, the proposed work utilises “Deep Learning” technology integrated with the proposed Vision and RADAR system. The Deep Learning technology can learn representations from labelled pixels; hence it does not depend on background pixels. The Deep 3 | P a g e Learning technology can classify, detect and localise objects at a Level Crossing area. It can classify and differentiate between a child and a small inanimate object, which was impossible with traditional algorithms. The system can detect an object regardless of its position, orientation and scale without any additional training because it learns representation from the data and does not rely on background pixels. The proposed system e.g., Deep Learning technology is integrated with the existing Vision System and RADAR installed at a Level Crossing, hence implementation cost is significantly reduced as well. The proposed work address two main aspects of training a model using Deep Learning technology; training from scratch and training using Transfer Learning techniques. Results are demonstrated for Image Classification, Object Detection and micro-Doppler signals from RADAR. An architecture of Convolutional Neural Network from scratch is trained consisting of Input Layer, Convolution, Pooling and Dropout Layer. The model achieves an accuracy of about 66.78%. Different notable models are trained using Transfer Learning techniques and their results are mentioned along with the MobileNet model, which achieves the highest accuracy of 91.9%. The difference between Image Classification and Object Detection is discussed and results for Object Detection are mentioned as well, where the Loss metrics are used to evaluate the performance of the Object Detector. MobileNet achieves the smallest loss metric of about 0.092. These results clearly show the effectiveness and preferability of these models for their applicability at Level Crossings. Another Convolutional Neural Network is trained using micro-Doppler signatures from the Radar system. The model trained using the micro-Doppler signature achieved an accuracy of 92%. The present work also addresses the Risk Assessment associated with the installation and maintenance of the system using Deep Learning technology. RAMS (Reliability, Availability, Maintainability and Safety) management system is used to address the General and Specific Risks associated with the sensing system integrated with the Deep Learning technology. Finally, the work is concluded with the preferred choice, its application, results and associated Risk Assessment. Deep Learning is an evolving field with new improvements being introduced constantly. Any new challenges and problems should be monitored regularly. Some future work is discussed as well. To further improve the model's accuracy, the dataset from the same distribution should be gathered with the cooperation of relevant Railway authorities. Also, the RADAR dataset could be generated rather than simulated to further include diversity and avoid any biases in the dataset during the training process. Also, the proposed system can be implemented and used in different applications within the Rail Industry e.g., passenger census and classification of passengers at the platform as discussed in the work

Influence of design parameters on the short-circuit ruggedness of SiC Power MOSFETs

This work aims to present an investigation on short-circuit (SC) failure behaviour of SiC Power MOSFETs due to the onset of thermal runaway. As inferable from experimental outcomes, it is related to the formation of hotspot, whose exact location is mainly unpredictable and dictated by device structure and design parameters non-uniformities. TCAD simulations were performed to examine the impact of some parameters mismatch on hotspot formation and failure occurrenc

Short-circuit robustness of parallel SiC MOSFETs and fail-safe mode strategy

International audienceSilicon carbide (SiC) power MOSFETs exhibit some key differences compared with Silicon (Si) MOSFETs and IGBTs. In particular, both their intrinsic (i.e., material technology related) and extrinsic (i.e., device generation related) features-set implies, on the one hand, higher stress levels of the single chip during a short-circuit and, on the other hand, a greater spread in the value of some of the main electro-thermal parameters affecting the transistor performance during this stressful transient event. Thus, this paper proposes a thorough experimental analysis of the short-circuit robustness of parallel connected SiC Power MOSFETs, taking into account the actual distribution in their parameters. The overall aim is twofold: producing de-rating guidelines for multi-chip structures and developing validated strategies for ensuring new and original soft-fail (or fail-safe) modalities in the application, as a result of both single and repetitive pulse degradation

VTH subthreshold hysteresis technology and temperature dependence in commercial 4H-SiC MOSFETs

VTH subthreshold hysteresis measured in commercially available 4H-SiC MOSFET is more pronounced in trench than in planar ones. All planar devices from different manufacturers exhibit an inverse temperature dependence, with the hysteresis amplitude reducing as the temperature increases, whereas all trench devices from different manufacturers exhibit the opposite behaviour. A physical interpretation is proposed, based on experimental evidence, which demonstrates that temperature dependence of the VTH subthreshold hysteresis is related to the technology. The findings are relevant to the ongoing discussion on SiC bespoke validation standards development and contribute important new insight

SiC MOSFET device parameter spread and ruggedness of parallel multichip structures

This paper presents a preliminary study of the impact of device electro-thermal parameter spread and temperature variation on the robustness of SiC MOSFET parallel multi-chip power switch architectures. Reference is made to 1200 V – 80 mΩ rated commercial devices. Some major parameters are identified and selected, presenting experimental evidence of their impact during transient overload events. An advanced physics-based simulation model is then employed to extend the analysis to a more comprehensive set of parameters and operational conditions

Static and dynamic TSEPs of SiC and GaN transistors

This paper investigates the static and dynamic temperature sensitive electrical parameters (TSEPs) for both SiC and GaN transistors. It is shown that both the qualitative and quantitative temperature characteristics of these parameters are various when different type of transistors are concerned. This finding can be used to select the most appropriate temperature sensitive parameter for the device under specific situation. In this paper, two types of transistors, SiC SCT2080KE MOSFET and GaN PGA26E19BA HEMT are evaluated and compared in terms of six TSEPs, including source-drain reverse bias voltage (VSD), static on-resistance (RDS,ON), gate threshold voltage (VGS(TH)), transconductance (gm), dIDS/dt switching transients and gate current (IG). Then, these TSEPs are compared using four criteria: temperature sensitivity, linearity, material and the capability of on-line temperature monitorin

V TH -Hysteresis and Interface States Characterisation in SiC Power MOSFETs with Planar and Trench Gate

International audienceThis paper contributes to investigations on the threshold-voltage (VTH) hysteresis in SiC power MOSFETs. Such effect is of relevance mainly for sub-threshold operation of the devices, but needs to be told apart from stress-related VTH-drift phenomena for technology maturity and reliability validation goals. Important differences exist in commercially available devices, particularly in relation to their gate technology, planar or trench, the latter also showing a marked temperature dependence of the hysteretic range. Based on the experimental characterization of the interface capacitance and charge, this paper puts forward a methodology for determining the types of traps affecting the various devices, with the aim of contributing a tool to assist driving of technological maturity in future generation devices. This paper also shows the potential of capacitance hysteresis measurement to the estimation of the distribution of interface