15 research outputs found
0.5 V log-domain realization of tinnitus detection system
A low-voltage tinnitus detection system using log-domain technique has been introduced in this paper. The design offers the advantages of resistorless design, electronic tunability of performance characteristics, and less complexity than the reported ones. The performance of the tinnitus detector has been verified by HSPICE simulation software using the parameters of TSMC CMOS 130 nm process
Realization of Integrable Low- Voltage Companding Filters for Portable System Applications
Undoubtedly, today’s integrated electronic systems owe their remarkable performance
primarily to the rapid advancements of digital technology since 1970s. The various
important advantages of digital circuits are: its abstraction from the physical details of
the actual circuit implementation, its comparative insensitiveness to variations in the
manufacturing process, and the operating conditions besides allowing functional
complexity that would not be possible using analog technology. As a result, digital
circuits usually offer a more robust behaviour than their analog counterparts, though
often with area, power and speed drawbacks. Due to these and other benefits, analog
functionality has increasingly been replaced by digital implementations.
In spite of the advantages discussed above, analog components are far from
obsolete and continue to be key components of modern electronic systems. There is
a definite trend toward persistent and ubiquitous use of analog electronic circuits in
day-to-day life. Portable electronic gadgets, wireless communications and the
widespread application of RF tags are just a few examples of contemporary
developments. While all of these electronic systems are based on digital circuitry,
they heavily rely on analog components as interfaces to the real world. In fact, many
modern designs combine powerful digital systems and complementary analog
components on a single chip for cost and reliability reasons. Unfortunately, the design
of such systems-on-chip (SOC) suffers from the vastly different design styles of
analog and digital components. While mature synthesis tools are readily available for
digital designs, there is hardly any such support for analog designers apart from wellestablished
PSPICE-like circuit simulators. Consequently, though the analog part
usually occupies only a small fraction of the entire die area of an SOC, but its design
often constitutes a major bottleneck within the entire development process.
Integrated continuous-time active filters are the class of continuous-time or
analog circuits which are used in various applications like channel selection in radios,
anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a
filter is the dynamic range; this is the ratio of the largest to the smallest signal that can
be applied at the input of the filter while maintaining certain specified performance.
The dynamic range required in the filter varies with the application and is decided by
the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the
capacitor area of an integrated active filter increases in proportion to its dynamic
range. This situation is incompatible with the needs of integrated systems, especially
battery operated ones. In addition to this fundamental dependence of power dissipation
on dynamic range, the design of integrated active filters is further complicated by the
reduction of supply voltage of integrated circuits imposed by the scaling down of
technologies to attain twin objective of higher speed and lower power consumption in
digital circuits. The reduction in power consumption with decreasing supply voltage
does not apply to analog circuits. In fact, considerable innovation is required with a
reduced supply voltage even to avoid increasing power consumption for a given signal
to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer.
A technique which has attracted the attention of circuit designers as a possible
route to filters with higher dynamic range per unit power consumption is
“companding”. Companding (compression-expansion) filters are a very promising
subclass of continuous-time analog filters, where the input (linear) signal is initially
compressed before it will be handled by the core (non-linear) system. In order to
preserve the linear operation of the whole system, the non-linear signal produced by
the core system is converted back to a linear output signal by employing an
appropriate output stage. The required compression and expansion operations are
performed by employing bipolar transistors in active region or MOS transistors in
weak inversion; the systems thus derived are known as logarithmic-domain (logdomain)
systems. In case MOS transistors operated in saturation region are employed,
the derived structures are known as Square-root domain systems. Finally, the third
class of companding filters can also be obtained by employing bipolar transistors in
active region or MOS transistors in weak inversion; the derived systems are known as
Sinh-domain systems. During the last several years, a significant research effort has been already
carried out in the area of companding circuits. This is due to the fact that their main
advantages are the capability for operation in low-voltage environment and large
dynamic range originated from their companding nature, electronic tunability of the
frequency characteristics, absence of resistors and the potential for operations in varied
frequency regions.Thus, it is obvious that companding filters can be employed for implementing
high-performance analog signal processing in diverse frequency ranges. For example,
companding filters could be used for realizing subsystems in: xDSL modems, disk
drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked
loops, FM stereo demodulator, touch-tone telephone tone decoder and
crossover network used in a three-way high-fidelity loudspeaker etc.
A number of design methods for companding filters and their building blocks
have been introduced in the literature. Most of the proposed filter structures operate
either above 1.5V or under symmetrical (1.5V) power supplies. According to data that
provides information about the near future of semiconductor technology, International
Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital
circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of
analog integrated circuits is the usage of low-voltage building blocks that use a single
0.5-1.5V power supply.
Therefore, the present investigation was primarily concerned with the study and
design of low voltage and low power Companding filters. The work includes the
study about: the building blocks required in implementing low voltage and low power
Companding filters; the techniques used to realize low voltage and low power
Companding filters and their various areas of application.
Various novel low voltage and low power Companding filter designs have been
developed and studied for their characteristics to be applied in a particular portable
area of application. The developed designs include the N-th order universal
Companding filter designs, which have been reported first time in the open literature.
Further, an endeavor has been made to design Companding filters with orthogonal
tuning of performance parameters so that the designs can be simultaneously used for
various features. The salient features of each of the developed circuit are described.
Electronic tunability is one of the major features of all of the designs. Use of
grounded capacitors and resistorless designs in all the cases makes the designs suitable
for IC technology. All the designs operate in a low-voltage and low-power
environment essential for portable system applications.
Unless specified otherwise, all the investigations on these designs are based on the
PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The
performance of each circuit has been validated by comparing the characteristics
obtained using simulation with the results present in the open literature.
The proposed designs could not be realized in silicon due to non-availability of
foundry facility at the place of study. An effort has already been started to realize
some of the designs in silicon and check their applicability in practical circuits. At the
basic level, one of the proposed Companding filter designs was implemented using the
commercially available transistor array ICs (LM3046N) and was found to verify the
theoretical predictions obtained from the simulation results
0.5 V log-domain realization of tinnitus detection system
595-603A low-voltage tinnitus detection system using log-domain technique has been introduced in this paper. The design offers the advantages of resistorless design, electronic tunability of performance characteristics, and less complexity than the reported ones. The performance of the tinnitus detector has been verified by HSPICE simulation software using the parameters of TSMC CMOS 130 nm process
Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)
Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility
Design and Optimization of High Performance P3HT: PCBM Polymer Solar Cell Using P3HT Buffer Layer
In this paper, a novel structure of multilayer organic photovoltaic cell has been designed and simulated. The integration of Poly(3-hexylthiophene-2,5-diyl) (P3HT) buffer layer and Poly(9,9-bis(3’-(N,N-dimethyl) N- ethylammoinium propyl-2,7-fluorene)-alt-2,7-(9,9 dioctyl fluorene)) dibromide (PFN:BR) electron transport layer (ETL) in the proposed solar cell has improved the performance significantly. The various performance measuring parameters like power conversion efficiency (PCE), short circuit current (Jsc), open circuit voltage (Voc), fill factor (FF), quantum efficiency (QE) have improved significantly. Furthermore, the effect of different layer thickness, the density of traps and temperature on the proposed solar cell has been studied and the optimum value has been obtained. It has been observed that after optimizing the different parameters of the proposed structure, the performance measuring parameters shows an improvement of 14%, 33.3%, 200% and 300% in Voc FF, Jsc and PCE respectively over the reported organic solar cells. Further, a QE of about 90% is achieved in the proposed structure
Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) based ternary combinational logic circuits
The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility
Carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) based ternary combinational logic circuits
The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility
Resistive random access memory: introduction to device mechanism, materials and application to neuromorphic computing
The modern-day computing technologies are continuously undergoing a rapid changing landscape; thus, the demands of new memory types are growing that will be fast, energy efficient and durable. The limited scaling capabilities of the conventional memory technologies are pushing the limits of data-intense applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Resistive random access memory (RRAM) is one of the most suitable emerging memory technologies candidates that have demonstrated potential to replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. RRAM has grown in prominence in the recent years due to its simple structure, long retention, high operating speed, ultra-low-power operation capabilities, ability to scale to lower dimensions without affecting the device performance and the possibility of three-dimensional integration for high-density applications. Over the past few years, research has shown RRAM as one of the most suitable candidates for designing efficient, intelligent and secure computing system in the post-CMOS era. In this manuscript, the journey and the device engineering of RRAM with a special focus on the resistive switching mechanism are detailed. This review also focuses on the RRAM based on two-dimensional (2D) materials, as 2D materials offer unique electrical, chemical, mechanical and physical properties owing to their ultrathin, flexible and multilayer structure. Finally, the applications of RRAM in the field of neuromorphic computing are presented.Published versionThis work was funded by Yayasan Universiti Teknologi PETRONAS (YUTP)-Fundamental Research Grant with cost centre 015LC0-245, and part of this research was carried out with the support of Grant NRF-CRP21-2018-0003
Morpho-Cultural and Pathogenic Variability of <i>Sclerotinia sclerotiorum</i> Causing White Mold of Common Beans in Temperate Climate
The present systematic research on cultural, morphological, and pathogenic variability was carried out on eighty isolates of Sclerotinia sclerotiorum collected from major common bean production belts of North Kashmir. The isolates were found to vary in both cultural and morphological characteristics such as colony color and type, colony diameter, number of days for sclerotia initiation, sclerotia number per plate, sclerotial weight, and size. The colony color ranged between white and off-white with the majority. The colony was of three types, in majority smooth, some fluffy, and a few fluffy-at-center-only. Colony diameter ranged between 15.33 mm and 29 mm after 24 h of incubation. The isolates took 4 to 7 days for initiation of sclerotia and varied in size, weight, and number per plate ranging between 14 and 51.3. The sclerotial arrangement pattern on plates was peripheral, sub peripheral, peripheral, and subperipheral, arranged at the rim and scattered. A total of 22 Mycelial compatibility groups (MCGs) were formed with seven groups constituted by a single isolate. The isolates within MCGs were mostly at par with each other. The six isolates representing six MCGs showed variability in pathogenicity with isolate G04 as the most and B01 as the least virulent. The colony diameter and disease scores were positively correlated. Sclerotia were observed to germinate both myceliogenically and carpogenically under natural temperate conditions of Kashmir. Germplasm screening revealed a single resistant line and eleven partially resistant lines against most virulent isolates