Simulation of transport in laterally gated junctionless transistors fabricated by local anodization with an atomic force microscope

In this paper, we have investigated the characteristics and transport features of junctionless lateral gate transistors via measurement and simulations. The transistor is fabricated using an atomic force microscopy (AFM) nanolithography technique on silicon-on-insulator (SOI) wafer. This work develops our previous examination of the device operation by using 3D numerical simulations to offer a better understanding of the origin of the transistor operation. We compare the experimental measurements and simulation results in the transfer characteristic and drain conductance. We also explore the behavior of the device in on and off states based on the variation of majority and minority carriers' density, electric-field components, and recombination/generation rate of carriers in the active region of the device. We show that the device is a normally on device that can force the current through a depleted region (off state) and uses bulk conduction instead of surface conduction. We also found that due to the lateral gate design, low-doped channel, and lack of the gate oxide the electrostatic squeezing of the channel effectively forces the device into the off state, but the current improvement by accumulation of carriers is not significant

Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography

The spark of aggressive scaling of transistors was started after the Moors law on prediction of device dimensions. Recently, among the several types of transistors, junctionless transistors were considered as one of the promising alternative for new generation of nanotransistors. In this work, we investigate the pinch-off effect in double gate and single gate junctionless lateral gate transistors. The transistors are fabricated on lightly doped (1015) p-type Silicon-on-insulator wafer by using an atomic force microscopy nanolithography technique. The transistors are normally on state devices and working in depletion mode. The behavior of the devices confirms the normal behavior of the junctionless transistors. The pinch-off effect appears at VG +2.0 V and VG +2.5 V for fabricated double gate and single structure, respectively. On state current is in the order of 10-9 (A) for both structures due to low doping concentration. The single gate and double gate devices exhibit an Ion/Ioff of approximately 105 and 106, respectively

Field effect in silicon nanostructure fabricated by atomic force microscopy nano lithography

The electrical property of silicon nano-structure is highly considered in nanoelectronics. In this context we investigate the field effect in nanostructure Junctionless p-type silicon nanowire transistor under the lateral gate voltage. The device fabricated by means of Atomic Force microscopy (AFM) nano lithography on Silicon on Insulator (SOI) wafer. I-V characteristic and the Drain/Source current under the lateral gate voltage investigated. The subthreshold swing measured and hysteresis effect observed for the old sample compared to new one

A simulation study of thickness effect in performance of double lateral gate junctionless transistors

The electrical behaviour of double lateral gate junctionless transistors, regarding to the variation of channel thickness is investigated, through 3-D numerical simulations. The simulation results explicitly show that how the device thickness affect the on and off current and threshold voltage behavior based on variation of the carriers density and recombination rates of the carriers. As the channel thickness is decreased, the amount of bulk neutral channel getting smaller which cause a decrease in the on state current. Meanwhile, the lateral gate influence on the channel is reinforced, which cause a decrease in leakage current in the off state. Threshold voltage is decreased as the channel thickness decreases. However, the recombination rate of carriers increases with decreasing the channel thickness, due to the accumulation of minority carries and shifted to the source side of the channel

Study of the side gate junctionless transistor in accumulation region

Mohd. Nizar Hamidon/ Jumiah Binti Hassan/ Arash Dehzangi/ Farhad Larki, Sawal Hamid Md Ali, Sabar Derita Hutagalung, Burhanuddin Yeop Majli

Impact of KOH etching on nanostructure fabricated by local anodic oxidation method

In this letter, we investigate the impact of potassium hydroxide (KOH) etching procedure on Silicon nanostructure fabricated by Atomic force microscopy on P-type Silicon-on-insulator. An electrochemical process, as the local anodic oxidation followed by two wet chemical etching steps, KOH etching for silicon removal and hydrofluoric etching for oxide removal, were implemented to fabricate the silicon nanostructures. The effect of the pure KOH concentrations (10% to 30% wt) on the quality of the surface is studied. The influence of etching immersing time in etching of nanostructure and SOI surface are considered as well. Impact of different KOH concentrations mixed with 10% IPA with reaction temperature on etch rate is investigated. The KOH etching process is elaborately optimized by 30%wt. KOH + 10%vol. IPA in appropriate time and temperature. The angle of the walls in etch pit for extracted nanowire reveals some deviation from the standard anisotropic etching

Effect of geometric parameters on the performance of p-type junctionless lateral gate transistors

This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension and based on that, the parameters such as threshold voltage, transconductance and resistance in saturation region are analyzed. In addition, simulation results provide a physical explanation for the variation of device characteristics given by the variation of geometric parameters, mainly based on investigation of the electric field components and the carries density variation. It is shown that, the variation of the carrier density is the main factor which affects the characteristics of the device when the device's thickness is varied. However, the electric field is mainly responsible for variation of the characteristics when the source/drain extension is changed

Numerical study of side gate junction-less transistor in on state

Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of V DS and V G on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain

Numerical investigation of channel width variation in junctionless transistors performance

Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors

Dependency of electrical characteristics on nano gap variation in pinch off lateral gate transistors

The variation of electrical characteristics with nano size air gap variation between gates and channel of a pinch off lateral gate transistor were investigated using 3D Technology Computer Aided Design. It is found that smaller nanosize gaps which can be formed by approaching the lateral gates to the channel can improve the switching performance of the device significantly. Devices with different air gap demonstrate same on state current and maximum transconductance of 0.05 μS, however the on/off current ratio (ION/IOFF) is varied by three orders of magnitude. The parameters such as electric field and band energy variation are investigated in order to explain the variation of electrical characteristics by air gap variation