Real-time Implementation of Space Vector Modulation using Arduino as a Low-cost Microcontroller for Three-phase Grid-connected Inverter

This work aims to facilitate the approach of a promising and fascinating technology, which is the photovoltaic (PV) energy, concerning the integration of PV systems to the utility grid from the control/synchronization point of view. Within this context, this paper gives a performance analysis of modeling and driving a two-level three-phase grid-connected PV system, in order to reduce the variations in frequency and phase, as a result, the synchronization between the inverter and the utility grid is accomplished and the correct function of the inverter is performed. MATLAB/Simulink software was utilized to develop the model of the suggested control algorithms. Then, as an interfacing device between the software and the inverter, the Arduino UNO microcontroller is proposed as a low-cost and simplified method to control the three-phase grid-connected inverte

A microsystem design for controlling a DC motor by pulse width modulation using MicroBlaze soft-core

This paper proposes a microsystem based on the field programmable gate arrays (FPGA) electronic board. The preliminary objective is to manipulate a programming language to achieve a control part capable of controlling the speed of electric actuators, such as direct current (DC) motors. The method proposed in this work is to control the speed of the DC motor by a purely embedded architecture within the FPGA in order to reduce the space occupied by the circuit to a minimum and to ensure the reliability of the system. The implementation of this system allows the embedded MicroBlaze processor to be installed side by side with its memory blocks provided by Xilinx very high-speed integrated circuit (VHSIC) hardware description language (VHDL), Embedded C. The control signal of digital pulse-width modulation pulses is generated by an embedded block managed by the same processor. This potential application is demonstrated by experimental simulation on the Vertix5 FPGA chip

EVALUATION ET AMELIORATION D'UN SYSTEME DE TATOUAGE AUDIO BASE SUR LA TECHNIQUE DE TATOUAGE PAR INSERTION D’ECHO

De nos jours le traitement des fichiers numériques est devenu très répandu. Les outils et logiciels pour dupliquer et redistribuer les fichiers numériques sont disponibles pour tout le monde et accessibles à faible coûts. Dans ce contexte, de nombreuses techniques ont vu le jour afin de contribuer à la protection de la propriété intellectuelle et lutter contre le piratage. Parmi, ces techniques nous trouvons les techniques de tatouage numérique des signaux, dit aussi WATERMARKING.Dans ce papier, nous avons réalisé la conception d’un système de tatouage par insertion d’écho et étudier ses performances par simulation sur MATLAB. L'idée principale de cette méthode est de cacher des données à l’intérieur d’un signal en insérant un écho de ce signal avec le retard approprié. Les tests de perceptibilité montrent que les filigranes sont imperceptibles. Les tests de fidélité montrent que la quantité de distorsion introduite par le tatouage est faible. Les tests de robustesse révèlent une bonne réponse face aux distorsions de signal les plus usuels. Les informations cachées sont toujours détectables et récupérables

Audio Watermarking Systems - Design, Implementation and Evaluation of an Echo Hiding Scheme Using Subjective Tests and Common Distortions

Today's digital media have made the product (digital content) very flexible and diminished the cost of its distribution. However, it contributes on piracy explosion as digital content can be duplicated and re-distributed at virtually no cost. Watermarking technology appears in order to protect the intellectual property and fight the piracy. It consists on embedding data like copyright labels inside a data source without changing its perceptual quality. In audio domain, watermarking techniques rely on the imperfection of the human auditory system in order to embed data. In this paper, we completed a design based on echo hiding technique and implement it in MATLAB. The main idea of this method is to embed data into an original signal by introducing an echo with the appropriate delay. Subjective listening tests reveal that the watermarks are imperceptible. Fidelity tests show that quantity of distortion imposed by watermarks on a signal is small. Robustness tests against common signal processing reveal good responses. The watermark information is always detectable and recoverable

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical designers and electronic design automation (EDA) providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR). An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP) technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS) and total negative slack (TNS) improved up to 13% and 56%, respectively, compared to the baseline flow

A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%

A New Photovoltaic Blocks Mutualization System For Micro-Grids Using An Arduino Board And Labview

The photovoltaic systems are often employed into micro-grids; Micro-grids are small power grids designed to provide a reliable and better power supply to a small number of consumers using renewable energy sources.This paper deals with DC micro-grids and present a new system of monitoring and sharing electricity between homes equipped with photovoltaic panels (PV) in the goal to reduce the electrical energy waste. The system is based on dynamic sharing of photovoltaic blocks through homes in stand-alone areas, using an arduino board for controlling the switching matrix. The LABVIEW program is used to further process and display collected data from the system in the PC screen. A small-scale prototype has been developed in a laboratory to proof the concept. This prototype demonstrates the feasibility and functionality of the system