4 research outputs found
Impact of Salicide and Source/Drain Implants on Leakage Current and Sheet Resistance in 45nm NMOS Device
In this paper, we investigate the impact of Source/Drain (S/D) implant and salicide on poly sheet resistance (RS) and leakage current (I Leak ) in 45nm NMOS device performance. The experimental studies were conducted under varying four process parameters, namely Halo implant, Source/Drain Implant, Oxide Growth Temperature and Silicide Anneal Temperature. Taguchi Method was used to determine the settings of process parameters. The level of importance of the process parameters on the RS and I Leak were determined by using analysis of variance (ANOVA). The fabrication of the devices was performed by using fabrication simulator of ATHENA. The electrical characterization of the device was implemented by using electrical characterization simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing the process parameters. The optimum process parameter combination was obtained by using the analysis of signal-tonoise (S/N) ratio. In this research, the most effective process parameters with respect to poly sheet resistance and leakage current are silicide anneal temperature (88%) and S/D implant (62%) respectively. Whereas the second ranking factor affecting the poly sheet resistance and leakage current are S/D implant (12%) and silicide anneal temperature (20%) respectively. As conclusions, S/D implant and silicide annealtemperature have the strongest effect on the response characteristics. The results show that the R S and I Leak after optimizations approaches are 42.28□□ and 0.1186mA/□m respectivel
Optimal solution in producing 32-nm CMOS technology transistor with desired leakage current
The objective of this paper is to optimize the process parameters of 32-nm
CMOS process to get minimum leakage current. Four process parameters were chosen,
namely: (i) source-drain implantation, (ii) source-drain compensation implantation,
(iii) halo implantation time, and (iv) silicide annealing time. The Taguchi method
technique was used to design the experiment. Two noise factors were used that consist of
four measurements for each row of experiment in the L9 array, thus leading to a set of
experiments consisting of 36 runs. The simulator of ATHENA and ATLAS were used for
MOSFET fabrication process and electrical characterization, respectively. The results
clearly show that the compensation implantation (46%) has the most dominant impact on
the resulting leakage current in NMOS device, whereas source-drain (S/D) implantation
was the second ranking factor (35%). The percent effects on signal-to-noise ratio (SNR)
of silicide annealing temperature and halo implantation are much lower being 12% and
7%, respectively. For the PMOS device, halo implantation was defined as an adjustment
factor because of its minimal effect on SNR and highest on the means (43%). Halo
implantation doping as the optimum solution for fabricating the 32-nm NMOS transistor
is 2.38×10¹³atom/cm³. As conclusion, this experiment proves that the Taguchi analysis
can be effectively used in finding the optimum solution in producing 32-nm CMOS
transistor with acceptable leakage current, well within International Technology
Roadmap for Semiconductor (ITRS) prediction
Control Factors Optimization on Threshold Voltage and Leakage Current in 22 nm NMOS Transistor Using Taguchi Method
In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-to-Noise Ratio (SNR) analysis uses the Nominal-the-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-the-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/µm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS)