34 research outputs found
Crosstalk suppression in a 650-V GaN FET bridgeleg converter using 6.7-GHz active gate driver
Investigation of a parasitic-inductance reduction technique for through-hole packaged power devices
Probing Techniques for GaN Power Electronics:How to Obtain 400+ MHz Voltage and Current Measurement Bandwidths without Compromising PCB Layout
Investigating GaN power device double-pulse testing efficacy in the face of VTH-shift, dynamic Rdson, and temperature variations
Use of an NSGA-II Genetic Algorithm and Active Gate Driving to Improve Simulated GaN Power Electronic Switching Waveforms
Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance
A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays