Computationally efficient, one-pass algorithm for morphological filters

International audienceMany useful morphological filters are built as long concatenations of erosions and dilations: openings, closings, size distributions, sequential filters, etc. This paper proposes a new algorithm implementing morphological dilation and erosion of functions. It supports rectangular structuring element, runs in linear time w.r.t. the image size and constant time w.r.t. the structuring element size, and has minimal memory usage. It has zero algorithm latency and processes data in stream. These properties are inherited by operators composed by concatenation, and allow their efficient implementation. We show how to compute in one pass an Alternate Sequential Filter (ASF(n)) regardless the number of stages n. This algorithm opens the way to such time-critical applications where the complexity and memory requirements of serial morphological operators represented a bottleneck limiting their usability. (C) 2011 Elsevier Inc. All rights reserved

Grey-scale 1-D dilations with spatially-variant structuring elements in linear time

Full text also available online for free at http://www.eurasip.org/Proceedings/Eusipco/Eusipco2008/International audienceSpatially variant morphological operators can significantly improve filtering capabilities or object detection score of various applications. Whereas an effort has been made to define the theoretical background, the efficient implementation of adaptable algorithms remained far less considered. In this paper, we present an efficient,one-scan, linear algorithm for 1-D grey-scale dilations/erosions with spatially variant structuring elements. The proposed algorithm processes data in stream, can work in place and produces results with minimal latency. The computing time is independent of the structuring element size

Efficient Hardware Architectures and Algorithms for Embedded Vision Systems

PrésentationAbstract : In this talk we develop three main axes i) design of efficient hardware architectures, ii) computational efficient algorithms targeted for embedded vision systems and iii) hardware support for self-aware computing.We will introduce recent advances within the unifying framework of mathematical morphology. We propose a first morphological processor with arbitrarily large neighborhoods. It allows to obtain previously unachieved performances for serially composed morphological filters, geodesical and conditional operators. The cited processor is based on a novel algorithm formulation of morphological dilation. Finally, the applicative domain will be illustrated in scene understanding context for self aware embedded computing

Texture Analysis with Arbitrarily Oriented Morphological Opening and Closing

13 pagesThis paper presents a fast, streaming algorithm for 1-D morphological opening on 2-D support. The algorithm is further extended to compute the complete size distribution during a single image run. The Structuring Element (SE) can be oriented under arbitrary angle that allows us to perform different orientation-involved image analysis, such as local angle extraction, directional granulometries, \etc The algorithm processes an image in constant time irrespective of the SE orientation and size, with a minimal latency and very low memory requirements. Regardless the SE orientation, it reads and writes data strictly sequentially in the horizontal scan order. Aforementioned properties allow an efficient implementation in embedded hardware platforms that opens a new opportunity of a parallel computation, and consequently, a significant speed-up

P2IP: A novel low-latency Programmable Pipeline Image Processor

International audienceThis paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P 2 IP. The P 2 IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurabil-ity of the P 2 IP enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the P 2 IP is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the P 2 IP can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications

Self-Adaptive Architecture for Multi-sensor Embedded Vision System

International audienceArchitectural optimization for heterogeneous multi-sensor processing is a real technological challenge. Most of the vision systems involve only one single color sensor and they do not address the heterogeneous sensors challenge. However, more and more applications require other types of sensor in addition, such as infrared or low-light sensor, so that the vision system could face various luminosity conditions. These heterogeneous sensors could differ in the spectral band, the resolution or even the frame rate. Such sensor variety needs huge computing performance , but embedded systems have stringent area and power constraints. Reconfigurable architecture makes possible flexible computing while respecting the latter constraints. Many reconfigurable architectures for vision application have been proposed in the past. Yet, few of them propose a real dynamic adaptation capability to manage sensor heterogeneity. In this paper, a self-adaptive architecture is proposed to deal with heterogeneous sensors dynamically. This architecture supports on-the-fly sensor switch. Architecture of the system is self-adapted thanks to a system monitor and an adaptation controller. A stream header concept is used to convey sensor information to the self-adaptive architecture. The proposed architecture was implemented in Altera Cyclone V FPGA. In this implementation, adaptation of the architecture consists in Dynamic and Partial Reconfiguration of FPGA. The self-adaptive ability of the architecture has been proved with low resource overhead and an average global adaptation time of 75 ms

Stream implementation of serial morphological filters with approximated polygons

ISBN : 978-142448157-6International audienceThis paper describes an original stream implementation of serially composed morphological filters using approximated flat polygons. It strictly respects a sequential data access. Results are obtained with minimal latency while operating within minimal memory space; even for very large neighborhoods. This is interesting for serially composed advanced filters, such as Alternating Sequential Filters or granulometries. We show how the dedicated implementation on an FPGA allows obtaining a previously unequaled performance, opening an opportunity to use these operators in time-critical, high-end applications

Fast and efficient FPGA implementation of connected operators

International audienceThe Connected Component Tree (CCT)-based operators play a central role in the development of new algorithms related to image processing applications such as pattern recognition, video-surveillance or motion extraction. The CCT construction, being a time consuming task (about 80% of the application time), these applications remain far-off mobile embedded systems. This paper presents its efficient FPGA implementation suited for embedded systems. Three main contributions are discussed: an efficient data structure proposal adapted to representing the CCT in embedded systems, a memory organization suitable for FPGA implementation by using on-chip memory and a customizable hardware accelerator architecture for CCT-based applications

Auto-Adaptive Multi-Sensor Architecture

International audienceTo overcome luminosity problems, modern embedded vision systems often integrate technologically heterogeneous sensors. Also, it has to provide different functionalities such as photo or video mode, image improvement or data fusion, according to the user environment. Therefore, nowadays vision systems should be context-aware and adapt their performance parameters automatically. In this context, we propose a novel auto-adaptive architecture enabling on-the-fly and automatic frame rate and resolution adaptation by a frequency tuning method. This method also intends to reduce power consumption as an alternative to existing power gating method. Performance evaluation in a FPGA implementation demonstrates an inter-frame adaptation capability with a relative low area overhead. I. INTRODUCTION From decades, the ability of computer vision systems increases thanks to the multiplication of integrated sensors. Multi-sensor systems enable many high-level vision applications such as stereo vision, data fusion [1] or 3D stereo view [2]. Also smart camera networks take advantage of the multi-sensor concept for large-scale surveillance applications [3]. More and more vision systems involve several heterogeneous sensors such as color, infrared or intensified low-light sensor [4] to overcome the variable luminosity conditions or improve the application robustness. Frequently, the considered vision system accomplishes various tasks such as video streaming, photo capture or high level processing (i.e. face detection, object tracking, ...). Each one of these tasks imposes different performance computing ability to the hardware resources, according to the applicative context and used sensor. That is why, nowadays vision systems have to be context-aware and to possess the ability to adapt their performance according to the user environment [5]. Fig. 1 illustrates the differences between video and photo user mode parameters: latency, frame rate, resolution, image quality and power consumption. While a video mode needs a high frame rate and low latency, a photo mode rather expects a higher resolution and higher image quality. In this context, we expect the system architecture adapt itself on-the-fly to the required frame rate or resolution while minimizing the use-case transition time when the user mode changes. In addition, the frame rate and the resolution of the involved sensors are not supposed to be known in advance. Numerous adaptable architectures exist for high-performance image processing [6]–[8] and also even for energy aware heterogeneous vision systems [2], they do not enable such dynamic adaptation of the frame rate or the resolution. In this paper, we propose a novel pixel frequency tuning approach for heterogeneous multi-sensor vision systems. Th

Memory System for a Dynamically Adaptable Pixel Stream Architecture

International audienceNowadays, embedded vision systems have to face new hard requirements involved by modern applications: realtime processing of high resolution images issued by multiple image sensors. Recently, a new adaptable ring-based interconnection network on chip has been proposed. Based on adaptive datapath, it allows handling of multiple parallel pixel streams. In this paper, we present a new hierarchical memory system proposed for this adaptable ring-based architecture. The design of its different levels is discussed and we show how the memory system adapts dynamically with respect to the datapath and data access management in the interconnection network. We also present the timing performance and area occupation measured on an FPGA prototype