Otimização e melhoria da modulação comportamental para os interfaces de E/S analógica e de sinal misto de alta velocidade

Doutoramento em Engenharia ElectrotécnicaA integridade do sinal em sistemas digitais interligados de alta velocidade, e avaliada através da simulação de modelos físicos (de nível de transístor) é custosa de ponto vista computacional (por exemplo, em tempo de execução de CPU e armazenamento de memória), e exige a disponibilização de detalhes físicos da estrutura interna do dispositivo. Esse cenário aumenta o interesse pela alternativa de modelação comportamental que descreve as características de operação do equipamento a partir da observação dos sinais eléctrico de entrada/saída (E/S). Os interfaces de E/S em chips de memória, que mais contribuem em carga computacional, desempenham funções complexas e incluem, por isso, um elevado número de pinos. Particularmente, os buffers de saída são obrigados a distorcer os sinais devido à sua dinâmica e não linearidade. Portanto, constituem o ponto crítico nos de circuitos integrados (CI) para a garantia da transmissão confiável em comunicações digitais de alta velocidade. Neste trabalho de doutoramento, os efeitos dinâmicos não-lineares anteriormente negligenciados do buffer de saída são estudados e modulados de forma eficiente para reduzir a complexidade da modelação do tipo caixa-negra paramétrica, melhorando assim o modelo standard IBIS. Isto é conseguido seguindo a abordagem semi-física que combina as características de formulação do modelo caixa-negra, a análise dos sinais eléctricos observados na E/S e propriedades na estrutura física do buffer em condições de operação práticas. Esta abordagem leva a um processo de construção do modelo comportamental fisicamente inspirado que supera os problemas das abordagens anteriores, optimizando os recursos utilizados em diferentes etapas de geração do modelo (ou seja, caracterização, formulação, extracção e implementação) para simular o comportamento dinâmico não-linear do buffer. Em consequência, contributo mais significativo desta tese é o desenvolvimento de um novo modelo comportamental analógico de duas portas adequado à simulação em overclocking que reveste de um particular interesse nas mais recentes usos de interfaces de E/S para memória de elevadas taxas de transmissão. A eficácia e a precisão dos modelos comportamentais desenvolvidos e implementados são qualitativa e quantitativamente avaliados comparando os resultados numéricos de extracção das suas funções e de simulação transitória com o correspondente modelo de referência do estado-da-arte, IBIS.Signal integrity (SI) simulation of high-speed digital interconnected system via transistor level models is computational expensive (e.g. CPU time and memory storage), and requires the availability of physical details information of device’s internal structure. This scenario raises the interest for a behavioral modeling alternative which describes the device’s operation characteristics based on the observed input/output (I/O) electrical signal. I/O buffers that interface memory’s interconnects have major share in the computational load containing a very active complex functional part and high numbers of pins. Particularly, output buffers/drivers are forced to distort the I/O signals due to their nonlinear dynamics. In this concern, they constitute the integrated circuit (IC) bottleneck of ensuring reliable data transmission in the high-speed digital communication link. In this PhD work, the previously neglected driver’s nonlinear dynamic effects are efficiently captured to significantly reduce the state of the art black-box parametric modeling complexities and enhance the input/output buffers information specifications (IBIS). This is achieved by following the gray-box approach that merges the features of the black-box model’s formulation, the analysis of the observed I/O electrical signals and the buffer’s physical structure properties under practical operation conditions. This approach leads to physically inspired behavioral model’s construction procedure that overcomes the issues of the previous modeling approaches by optimizing the resources used at different model’s generation steps (i.e. characterization, formulation, extraction, and implementation) to mimic the driver’s nonlinear dynamic behavior. Moreover, the most important achievement is the development of a new two-port analog behavioral model for overclocking simulation that copes with the recent trends in I/O memory interfaces characterized by higher data rate transmission. The effectiveness and the accuracy of the developed and implemented behavioral models are qualitatively and quantitatively assessed by comparing the numerical results of their functions extraction and transient simulation to the ones simulated and extracted with transistor level models and the state of the art IBIS in order to validate their predictive and the generalization capabilities

Omnidirectional WPT and data communication for electric air vehicles: feasibility study

This paper investigates the feasibility of using the three dimensional omnidirectional inductive channel for power transfer and as a power line communication PLC for ground-based vehicle, electric air vehicle or space applications, the simulation results is performed by the advanced design system software using lumped equivalent circuit model. The power transfer efficiency determined based on multiport scattering (S)-parameters numerical simulation results while the theoretical channel capacity is calculated based on Matlab software as a function of the coupling coefficient considering an additive white Gaussian noise . Furthermore, the magnetic field distribution is evaluated as function of the misalignment angle θ between the receiver and the three orthogonal transmitters coils

Characterization of a Two-Coil Channel Considering Misalignment Scenarios

Publisher Copyright: © 2022 by the authors. Licensee MDPI, Basel, Switzerland.WPT system performances highly depend on the misalignment scenarios of the transmitter or the receiver coil. In this contribution, the authors analyze the effect of the misalignment influencing factors of the integrated WPT-PLC system receiving coil on the system performances. The simulations and experimental analysis are based on power efficiency and channel capacity metrics. The simulations are performed using finite element calculations in COMSOL Multiphysics and Advanced Design System (ADS) from Keysight technology. By analyzing the results, maximum transferred power is reached under resonance conditions. For instance, the calculated efficiencies versus the misalignment cases of the WPT-PLC system varies (η = 86% to 60%) when d = [3 cm to 7 cm], s = [3 cm to 9 cm], and for a tilt angle θ ≤ 20 deg, while the optimal data rate C(bps) is achieved while appealing different data access points and under reasonable SNR value.publishersversionpublishe

Performance Enhancement of Large Crossbar Resistive Memories With Complementary and 1D1R-1R1D RRAM Structures

The paper proposes novel solutions to improve the signal and thermal integrity of crossbar arrays of Resistive Random-Access Memories, that are among the most promising technologies for the 3D monolithic integration. These structures suffer from electrothermal issues, due to the heat generated by the power dissipation during the write process. This paper explores novel solutions based on new architectures and materials, for managing the issues related to the voltage drop along the interconnects and to thermal crosstalk between memory cells. The analyzed memristor is the 1 Diode - 1 Resistor memory. The two architectural solutions are given by a reverse architecture and a complementary resistive switching one. Compared to conventional architectures, both of them are also reducing the number of layers where the bias is applied. The electrothermal performance of these new structures is compared to that of the reference one, for a case-study given by a 4 × 4 × 4 array. To this end, a full-3D numerical Multiphysics model is implemented and successfully compared against other models in literature. The possibility of changing the interconnect materials is also analyzed. The results of this performance analysis clearly show the benefits of moving to these novel architectures, together with the choice of new materials

Memristor State-Space Embedding

This paper presents a procedure for the determination of the dimensionality of the state space of a memristive device. The state space dimensionality of a device corresponds to the minimum number of time delayed values/derivatives of the voltage and current required to represent the device dynamics for a specified set of inputs. The algorithm is based on the observed time domain voltage-current (i.e. input-output) data which is obtained by measurement. The determination of the state space dimensionality is important to achieve a single-valued input-output multivariate mapping between the device outputs as a function of the embedding variables. In this paper, this will be accomplished using an embedding technique, based on the false nearest neighbor principle

Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., VDD/VSS) and last stage (i.e., VDDQ/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions

Design and Realization of a Multiple Access Wireless Power Transfer System for Optimal Power Line Communication Data Transfer

In this contribution, the authors evaluate the possibility of using separated access points for power and data transfer in a coupled Wireless Power Transfer-Powerline Communication system. Such a system has been previously proposed by the authors for specific applications, in which Wireless Power Transfer (WPT) should take place in a system where data are transmitted over the power grid. In previous works the authors have performed lab tests on a two coils WPT system equipped with a set of filters to also allow an efficient data transfer. When a multiple coil WPT system is chosen, additional possibilities arise: the access point for power and data can be differentiated, with the aim of maintaining the designed power efficiency and increase data transfer capacity. In this study a four coils WPT system is thoroughly analyzed, modelled, implemented and measured, and a set of guidelines for the correct design (in terms of performance optimization) of the data transfer is given

Enhanced I/O Buffer Predriver Modeling under Power/Ground Supply Voltage Variation

This paper presents I/O buffer nonlinear behavioral modelling that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variation. Model structure and I/O device characterization along with extraction procedure are described. I/O buffer’s last stage is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The predriver’s mathematical model structure is derived from the analysis of the large signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure is considered in this work. Timing series data, which reflects the observed the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, is used to train the NN model. The proposed model is implemented in time domain solver and validated against reference transistor level (TL) model and the state of the art input-output buffer information specification (IBIS) behavioral model under different scenarios. The jitter analysis is performed using the eye diagram tool through analyzing its different metrics values