Interface Engineering Routes for a Future CMOS Ge-based Technology

We present an overview study of two germanium interface engineering routes, firstly a germanate formation via La2O3 and Y2O3, and secondly a barrier layer approach using Al2O3 and Tm2O3. The interfacial composition, uniformity, thickness, band gap, crystallinity, absorption features and valence band offset are determined using X-ray photoelectron spectroscopy, ultra violet variable angle spectroscopic ellipsometry, and high resolution transmission electron microscopy. The correlation of these results with electrical characterization data make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS.</jats:p

Atomic-layer deposited thulium oxide as a passivation layer on germanium

A comprehensive study of atomic-layer deposited thulium oxide (Tm2O3) on germanium has been conducted using x-ray photoelectron spectroscopy (XPS), vacuum ultra-violet variable angle spectroscopic ellipsometry, high-resolution transmission electron microscopy (HRTEM), and electron energy-loss spectroscopy. The valence band offset is found to be 3.05 ± 0.2 eV for Tm2O3/p-Ge from the Tm 4d centroid and Ge 3p3/2 charge-corrected XPS core-level spectra taken at different sputtering times of a single bulk thulium oxide sample. A negligible downward band bending of ∼0.12 eV is observed during progressive differential charging of Tm 4d peaks. The optical band gap is estimated from the absorption edge and found to be 5.77 eV with an apparent Urbach tail signifying band gap tailing at ∼5.3 eV. The latter has been correlated to HRTEM and electron diffraction results corroborating the polycrystalline nature of the Tm2O3 films. The Tm2O3/Ge interface is found to be rather atomically abrupt with sub-nanometer thickness. In addition, the band line-up of reference GeO2/n-Ge stacks obtained by thermal oxidation has been discussed and derived. The observed low reactivity of thulium oxide on germanium as well as the high effective barriers for holes (∼3 eV) and electrons (∼2 eV) identify Tm2O3 as a strong contender for interfacial layer engineering in future generations of scaled high-κ gate stacks on Ge

Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?

© 2018 IOP Publishing Ltd. In order to improve the low-frequency noise of input/output (I/O) p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a 5 nm SiO2/2 nm HfO2/5 nm TiN gate stack for DRAM applications, different post-deposition treatments have been investigated. Decoupled Plasma Nitridation with various strengths is compared with an SF6 plasma anneal. Wafers with and without an Al2O3 cap, serving as a threshold voltage shifter have also been included in the study. It is shown that the best results, i.e. the lowest 1/f noise magnitude, have been found for the SF6-treated I/O pMOSFETs, reaching in the best case a value comparable with SiO2/polycrystalline silicon reference devices.status: publishe

Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor–insulator–graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler–Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm−2 (limited by series resistance), and excellent current–voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices