Comparing a material circularity indicator to life cycle assessment: The case of a three-layer plastic packaging

International audienceThere is a serious need to assess the evolution of transitions from a linear to a Circular Economy (CE) using tools, metrics, and measurement indicators that not only are able to take into account the circularity, but also the other sustainability performances of products. Currently, most measurement tools do not lead to valuable decisions, as they do not capture the performance of the CE in its entirety, resulting in poorer performance on certain aspects, such as the environment. In addition, the lack of industry-specific indicators may hinder the adaptation of CE due to the different structures and functions of products. Consequently, this paper proposes a circularity indicator adapted from the Material Circularity Indicator (MCI) for the plastic industry, specifically Multi-layer Plastic Packaging (MPP). The adapted indicator is expanded based on the quality of recycled polymers by defining a new utility factor (X) as the polymers' intensity of re-use. It also highlights that it is necessary to combine a circularity indicator with Life Cycle Assessment (LCA) for viable end-of-life (EOL) management. To illustrate the use of the proposed indicator and the trade-offs between circularity and environmental impacts, a case study on three-layer plastic packaging is applied to two end-of-life scenarios (Incineration, and closed-loop mechanical recycling). The results show that an increase in material circularity generally decreases the environmental impacts. However, recycling was found to have a higher impact than incineration on some impact categories such as land use and freshwater eutrophication

Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow

In this paper we research an. FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node rising a retard getable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks. A second design iteration results in a 11)1 optimized ASIP with a VLIW instruction set which allowsfor high degree of parallelism among the functional units inside the ASIP and has dedicated instructions to accelerate typical packet processing tasks. This way, a single processor is capable of handling the complete throughput of a gigabit Ethernet link. To reach the target of a 10 Gbit/s Ethernet access node several processors operate in parallel in a multicore environment

Hardware accelaration of an RTP proxy server

More and more TVoIP services are emerging on the market using RTP to compensate for the dynamic routing. Interactive applications, however, still suffer from the network's long latency. Offloading to the access network offers a solution. In this paper we present an optimized hardware architecture for a proxy handling RTP packets delivering an acceleration ratio of over 440. The architecture has built-in support for Video-on-Demand, Time-Shifted TV and Fast Channel Change services, and has been successfully tested on a custom FPGA board

A scalable network ASIP enabling flow awareness in Ethernet access

In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an architecture optimized to handle flow processing tasks such as parsing, classification and packet manipulation. The VLIW instruction set allows for high degree of parallelism among the functional units inside the ASIP and has dedicated instructions to accelerate typical packet processing tasks. This way, a single processor is capable of handling the complete throughput of a gigabit Ethernet link. To reach the target of a 10 Gbit/s Ethernet access node several processors operate in parallel in a multicore environment. Apart from scalability, programmability is also an important feature. Therefore, the processor is developed using a retargetable tool suite, creating the hardware and an optimized C compiler out of a single processor description. 1

Mixed analogue/digital phase picking algorithm in oversampling burst-mode clock phase alignment

A novel mixed analogue/digital design of a phase picking algorithm in an oversampling clock phase recovery is presented. The proposed approach results in reduced processing time, improved integrability with analogue front-end and low noise generation. Simulations of a 10 Gbit/s burst-mode clock phase alignment circuit in a 0.25 mm SiGe BiCMOS process, show a simulated processing delay of only 280 ps

Fully DC-coupled 10Gb/s burst-mode PON prototypes and upstream experiments with 58ns overhead

This paper presents a chain of four fully DC-coupled 10Gb/s burst-mode prototypes operating with 58ns overhead for the first time. 10Gb/s upstream burst-mode experiments are performed without a time-critical reset signal from test equipment. (C) 2010 Optical Society of Americ