Ge2Sb2Te5 layer used as solid electrolyte in conductive-bridge memory devices fabricated on flexible substrate

7 pagesInternational audienceThis paper shows that the well-know chalcogenide Ge2Sb2Te5 (GST) in its amorphous state may be advantageously used as solid electrolyte material to fabricate Conductive-Bridge Random Access Memory (CBRAM) devices. GST layer was sputtered on preliminary inkjet-printed silver lines acting as active electrode on either silicon or plastic substrates. Whatever the substrate, the resistance switching is unambiguously attested at a nanoscale by means of conductive-atomic force microscopy (C-AFM) using a Pt-Ir coated tip on the GST surface acting as a passive electrode. The resistance change is correlated to the appearance or disappearance of concomitant hillocks and current spots at the surface of the GST layer. This feature is attributed to the formation/dissolution of a silver-rich protrusion beneath the AFM tip during set/reset operation. Beside, this paper constitutes a step toward the elaboration of crossbar memory arrays on flexible substrates since CBRAM operations were demonstrated on W/GST/Ag crossbar memory cells obtained from an heterogeneous fabrication process combining physical deposition and inkjet-printing

Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories

We present a new fully self-aligned single-electron memory with a single pair of nano floating gates, made of different materials (Si and Ge). The energy barrier that prevents stored charge leakage is induced not only by quantum effects but also by the conduction-band offset that arises between Ge and Si. The dimension and position of each floating gate are well defined and controlled. The devices exhibit a long retention time and single-electron injection at room temperature

Conductive Bridge Random Access Memory Devices Based on an Ecofriendly Solid Polymer Electrolyte

International audienc

Resistance controllability and variability improvement in a TaO x -based resistive memory for multilevel storage application

International audienceIn order to obtain reliable multilevel cell (MLC) characteristics, resistance controllability between the different resistance levels is required especially in resistive random access memory (RRAM), which is prone to resistance variability mainly due to its intrinsic random nature of defect generation and filament formation. In this study, we have thoroughly investigated the multilevel resistance variability in a TaOx-based nanoscale (<30 nm) RRAM operated in MLC mode. It is found that the resistance variability not only depends on the conductive filament size but also is a strong function of oxygen vacancy concentration in it. Based on the gained insights through experimental observations and simulation, it is suggested that forming thinner but denser conductive filament may greatly improve the temporal resistance variability even at low operation current despite the inherent stochastic nature of resistance switching process

Low-power resistive switching in Au/NiO/Au nanowire arrays

Arrays of vertical nanowires structured in Au/NiO/Au segments with 50 nm diameter are characterized by conductive atomic force microscopy to investigate unipolar resistive switching in NiO at the nanoscale. The switching cycles are characterized by extremely low power consumption down to 1.3 nW, which constitutes a significant improvement in nanowire-based resistive switching memory devices. The trend of the reset current as a function of the set resistance, typical of unipolar memories, is extended to a much wider current range than what is reported in literature, confirming the role of Joule heating in the reset process for very low reset currents

Degradation of floating gate memory reliability by few electron phenomena

International audienc

Resistance change in memory structures integrating CuTCNQ nanowires grown on dedicated HfO2 switching layer

International audienc