Elucidating the Photoresponse of Ultrathin MoS₂ Field-Effect Transistors by Scanning Photocurrent Microscopy

The mechanisms underlying the intrinsic photoresponse of few-layer (FL) molybdenum disulfide (MoS₂) field-effect transistors are investigated via scanning photocurrent microscopy. We attribute the locally enhanced photocurrent to band-bending-assisted separation of photoexcited carriers at the MoS₂/Au interface. The wavelength-dependent photocurrents of FL MoS₂ transistors qualitatively follow the optical absorption spectra of MoS₂, providing direct evidence of interband photoexcitation. Time and spectrally resolved photocurrent measurements at varying external electric fields and carrier concentrations establish that drift-diffusion currents dominate photothermoelectric currents in devices under bias

Low-Frequency Electronic Noise in Single-Layer MoS₂ Transistors

Ubiquitous low-frequency 1/<i>f</i> noise can be a limiting factor in the performance and application of nanoscale devices. Here, we quantitatively investigate low-frequency electronic noise in single-layer transition metal dichalcogenide MoS₂ field-effect transistors. The measured 1/<i>f</i> noise can be explained by an empirical formulation of mobility fluctuations with the Hooge parameter ranging between 0.005 and 2.0 in vacuum (<10^–5 Torr). The field-effect mobility decreased, and the noise amplitude increased by an order of magnitude in ambient conditions, revealing the significant influence of atmospheric adsorbates on charge transport. In addition, single Lorentzian generation-recombination noise was observed to increase by an order of magnitude as the devices were cooled from 300 to 6.5 K

Printed Indium Gallium Zinc Oxide Transistors. Self-Assembled Nanodielectric Effects on Low-Temperature Combustion Growth and Carrier Mobility

Solution-processed amorphous oxide semiconductors (AOSs) are emerging as important electronic materials for displays and transparent electronics. We report here on the fabrication, microstructure, and performance characteristics of inkjet-printed, low-temperature combustion-processed, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) grown on solution-processed hafnia self-assembled nanodielectrics (Hf-SANDs). TFT performance for devices processed below 300 °C includes >4× enhancement in electron mobility (μ_FE) on Hf-SAND versus SiO₂ or ALD-HfO₂ gate dielectrics, while other metrics such as subthreshold swing (SS), current on:off ratio (<i>I</i>_ON:<i>I</i>_OFF), threshold voltage (<i>V</i>_th), and gate leakage current (<i>I</i>_g) are unchanged or enhanced. Thus, low voltage IGZO/SAND TFT operation (<2 V) is possible with <i>I</i>_ON:<i>I</i>_OFF = 10⁷, SS = 125 mV/dec, near-zero <i>V</i>_th, and large electron mobility, μ_FE(avg) = 20.6 ± 4.3 cm² V^–1 s^–1, μ_FE(max) = 50 cm² V^–1 s^–1. Furthermore, X-ray diffraction analysis indicates that the 300 °C IGZO combustion processing leaves the underlying Hf-SAND microstructure and capacitance intact. This work establishes the compatibility and advantages of all-solution, low-temperature fabrication of inkjet-printed, combustion-derived high-mobility IGZO TFTs integrated with self-assembled hybrid organic–inorganic nanodielectrics

Reconnaissance et synthese vocale dans les telecommunications

SIGLECNRS-CDST / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Solution-Processed Self-Assembled Nanodielectrics on Template-Stripped Metal Substrates

The coupling of hybrid organic–inorganic gate dielectrics with emergent unconventional semiconductors has yielded transistor devices exhibiting record-setting transport properties. However, extensive electronic transport measurements on these high-capacitance systems are often convoluted with the electronic response of the semiconducting silicon substrate. In this report, we demonstrate the growth of solution-processed zirconia self-assembled nanodielectrics (Zr-SAND) on template-stripped aluminum substrates. The resulting Zr-SAND on Al structures leverage the ultrasmooth (r.m.s. roughness <0.4 nm), chemically uniform nature of template-stripped metal substrates to demonstrate the same exceptional electronic uniformity (capacitance ∼700 nF cm^–2, leakage current <1 μA cm^–2 at −2 MV cm^–1) and multilayer growth of Zr-SAND on Si, while exhibiting superior temperature and voltage capacitance responses. These results are important to conduct detailed transport measurements in emergent transistor technologies featuring SAND as well as for future applications in integrated circuits or flexible electronics

Solution-Processed Dielectrics Based on Thickness-Sorted Two-Dimensional Hexagonal Boron Nitride Nanosheets

Gate dielectrics directly affect the mobility, hysteresis, power consumption, and other critical device metrics in high-performance nanoelectronics. With atomically flat and dangling bond-free surfaces, hexagonal boron nitride (h-BN) has emerged as an ideal dielectric for graphene and related two-dimensional semiconductors. While high-quality, atomically thin h-BN has been realized via micromechanical cleavage and chemical vapor deposition, existing liquid exfoliation methods lack sufficient control over h-BN thickness and large-area film quality, thus limiting its use in solution-processed electronics. Here, we employ isopycnic density gradient ultracentrifugation for the preparation of monodisperse, thickness-sorted h-BN inks, which are subsequently layer-by-layer assembled into ultrathin dielectrics with low leakage currents of 3 × 10^–9 A/cm² at 2 MV/cm and high capacitances of 245 nF/cm². The resulting solution-processed h-BN dielectric films enable the fabrication of graphene field-effect transistors with negligible hysteresis and high mobilities up to 7100 cm² V^–1 s^–1 at room temperature. These h-BN inks can also be used as coatings on conventional dielectrics to minimize the effects of underlying traps, resulting in improvements in overall device performance. Overall, this approach for producing and assembling h-BN dielectric inks holds significant promise for translating the superlative performance of two-dimensional heterostructure devices to large-area, solution-processed nanoelectronics

Large-Area, Low-Voltage, Antiambipolar Heterojunctions from Solution-Processed Semiconductors

The emergence of semiconducting materials with inert or dangling bond-free surfaces has created opportunities to form van der Waals heterostructures without the constraints of traditional epitaxial growth. For example, layered two-dimensional (2D) semiconductors have been incorporated into heterostructure devices with gate-tunable electronic and optical functionalities. However, 2D materials present processing challenges that have prevented these heterostructures from being produced with sufficient scalability and/or homogeneity to enable their incorporation into large-area integrated circuits. Here, we extend the concept of van der Waals heterojunctions to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type amorphous indium gallium zinc oxide (a-IGZO) thin films that can be solution-processed or sputtered with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p–n heterojunctions exhibit antiambipolar transfer characteristics with high on/off ratios that are well-suited for electronic, optoelectronic, and telecommunication technologies

Investigation of Band-Offsets at Monolayer–Multilayer MoS₂ Junctions by Scanning Photocurrent Microscopy

The thickness-dependent band structure of MoS₂ implies that discontinuities in energy bands exist at the interface of monolayer (1L) and multilayer (ML) thin films. The characteristics of such heterojunctions are analyzed here using current versus voltage measurements, scanning photocurrent microscopy, and finite element simulations of charge carrier transport. Rectifying <i>I</i>–<i>V</i> curves are consistently observed between contacts on opposite sides of 1L/ML junctions, and a strong bias-dependent photocurrent is observed at the junction. Finite element device simulations with varying carrier concentrations and electron affinities show that a type II band alignment at single layer/multilayer junctions reproduces both the rectifying electrical characteristics and the photocurrent response under bias. However, the zero-bias junction photocurrent and its energy dependence are not explained by conventional photovoltaic and photothermoelectric mechanisms, indicating the contributions of hot carriers

Quantitatively Enhanced Reliability and Uniformity of High‑κ Dielectrics on Graphene Enabled by Self-Assembled Seeding Layers

The full potential of graphene in integrated circuits can only be realized with a reliable ultrathin high-κ top-gate dielectric. Here, we report the first statistical analysis of the breakdown characteristics of dielectrics on graphene, which allows the simultaneous optimization of gate capacitance and the key parameters that describe large-area uniformity and dielectric strength. In particular, vertically heterogeneous and laterally homogeneous Al₂O₃ and HfO₂ stacks grown via atomic-layer deposition and seeded by a molecularly thin perylene-3,4,9,10-tetracarboxylic dianhydride organic monolayer exhibit high uniformities (Weibull shape parameter β > 25) and large breakdown strengths (Weibull scale parameter, <i>E</i>_BD > 7 MV/cm) that are comparable to control dielectrics grown on Si substrates