A Preliminary Report on the Caltech ARPA Tester Project

No Abstract

The Sandia petaflops planner.

The Sandia Petaflops Planner is a tool for projecting the design and performance of parallel supercomputers into the future. The mathematical basis of these projections is the International Technology Roadmap for Semiconductors (ITRS, or a detailed version of Moore's Law) and DOE balance factors for supercomputer procurements. The planner is capable of various forms of scenario analysis, cost estimation, and technology analysis. The tool is described along with technology conclusions regarding PFLOPS-level supercomputers in the upcoming decade

A network architecture for Petaflops supercomputers.

If we are to build a supercomputer with a speed of 10{sup 15} floating operations per second (1 PetaFLOPS), interconnect technology will need to be improved considerably over what it is today. In this report, we explore one possible interconnect design for such a network. The guiding principle in this design is the optimization of all components for the finiteness of the speed of light. To achieve a linear speedup in time over well-tested supercomputers of todays' designs will require scaling up of processor power and bandwidth and scaling down of latency. Latency scaling is the most challenging: it requires a 100 ns user-to-user latency for messages traveling the full diameter of the machine. To meet this constraint requires simultaneously minimizing wire length through 3D packaging, new low-latency electrical signaling mechanisms, extremely fast routers, and new network interfaces. In this report, we outline approaches and implementations that will meet the requirements when implemented as a system. No technology breakthroughs are required

Taking ASCI Supercomputing to the End Game

The ASCI supercomputing program is broadly defined as running physics simulations on progressively more powerful digital computers. What happens if we extrapolate the computer technology to its end? We have developed a model for key ASCI computations running on a hypothetical computer whose technology is parameterized in ways that account for advancing technology. This model includes technology information such as Moore’s Law for transistor scaling and developments in cooling technology. The model also includes limits imposed by laws of physics, such as thermodynamic limits on power dissipation, limits on cooling, and the limitation of signal propagation velocity to the speed of light. We apply this model and show that ASCI computations will advance smoothly for another 10-20 years to an “end game ” defined by thermodynamic limits and the speed of light. Performance levels at the end game will vary greatly by specific problem, but will be in the Exaflops to Zettaflops range for currently anticipate

Testing and Structured Design

This paper describes part of an integrated circuit testing project carried out at Caltech between 1979 and 1982. The central theme and result of the project is a language or notation for describing tests for complex integrated circuits. The evolution of this test language has been guided by many considerations, including (1) its implementation in a working, interactive test system called FIFI, (2) its fit to ideas about the architecture of high-performance test instruments, and (3) its expressivity for a design-for-testability strategy for chip designs structured in the general style presented by Mead and Conway [1]

On the design of reversible QDCA systems.

This work is the first to describe how to go about designing a reversible QDCA system. The design space is substantial, and there are many questions that a designer needs to answer before beginning to design. This document begins to explicate the tradeoffs and assumptions that need to be made and offers a range of approaches as starting points and examples. This design guide is an effective tool for aiding designers in creating the best quality QDCA implementation for a system

Reversible L ogic for Supercomputing

This paper is ab out making reversib le logic a reali ty for supercomputing. Reversib le logic offers a way to ex ceed certain b asic limits on the performance of computers, yet a powerful case will have tob e made to justify its sub stantial dev elopment expense. This paper explores the limits of current, irreversib le logic for supercomputers, thus forming a threshold ab ove which reversib le logic is the only solution. Prob lems ab o ve this threshold are discussed, with the science and mitig ation of glob al warmingb eing discussed in detail. To further devel op the idea of using reversib le logic in supercomputing, a design for a 1 Zettaflops supercomputer as required for addressing glob al climate warming is presented. However, to create su ch a design requires deviations from the mainstream ofb oth the software for climate simulation and research directions of rever sib le logic. These deviations provide direction on how to make r eversib le logic practical