Upgrade of the L2 electronics in the CMS Muon Drift Tubes system

The excellent performance of the DT system during the past years is expected to be pursued at the increased luminosity, so the main motivation driving the DT upgrade is focused on improving the electronic system to maintain its reliability. The fulfillment of this project envisages to turn electrical signals into optical signals for a total number of 3500 optical channels that run at up to 480 Mb/s data rate. A Bit Error Rate (BER) of the order of 10−12 with a confidence level (CL) of 95% has been measured which ensures that an appropriate components choice has been made in view of the full boards production

The optical links for the trigger upgrade of the Drift Tube in CMS

The first phase of the upgrade of the electronics of Drift Tubes (DT) in the CMS experiment is reported. It consists of the translation of the readout and trigger data from electrical into optical and their transmission from the CMS experimental cavern to the counting room. Collecting the full information of the DT chambers in the counting room allows the development of new trigger hardware and algorithms

Epitaxial hybrid pixel with triggerless readout in 130nm Cmos technology for the Micro Vertex Detector of the Panda experiment

The Micro Vertex Detector (MVD) is the innermost one of the Panda experiment, sitting around the beam pipe. The sensors are arranged in a barrel section with two pixel and two strip layers, and 6 forward disks with mixed pixel and microstrip sensors. For the pixel detector part, a hybrid solution with thinned epitaxial sensors was chosen. The main requirements for the readout include: a pixel size of 100 · 100 μm2, an input charge measurement with 12 b that implies an amplitude resolution of 1 part out of 4096, a working frequency of 155.5MHz, and a triggerless acquisition. The readout of the pixel detector is based on a front end chip, named Topix, that is under development. The Asic will provide the time position with a resolution of 6.43 ns and a charge measurement with a Time Over Threshold (TOT) technique; it features a matrix of 116 · 110 pixel cell channels and 311 Mb/s serializers as output ports. A 130nm Cmos technology has been used to reduce the circuit size and to provide tolerance for the total dose, besides techniques against single event upset have been implemented. A Topix prototype with the full cell has been completely tested for radiation damage before and after irradiation, and a new release has been submitted to build an hybrid assembly. The stringent requirements in terms of space for the MVD lead to an architecture based on optical links. The GigaBit Transceiver (GBT) from CERN has been chosen as the baseline solution for the interface to the data acquisition. Low mass cables based on aluminium on polyimide are under development for the interconnections

Front end electronics for pixel detector of the PANDA MVD

ToPix 2.0 is a prototype in a CMOS 0.13 ¹m technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 ¹W/cell). In an area of 100¹m£100¹m each cell incorporates the analog and digital electronics necessary to amplify the detector signal and to digitize the time and charge information. The ASIC includes 320 pixel readout cells organized in four columns and a simplified version of the end of column readout

Hybrid pixels for the PANDA Micro-Vertex Detector

PANDA is a fixed target experiment that will be carried out at the future FAIR facility. The PANDA experiment will perform precise studies of antiproton-proton and antiproton-nuclei annihilations, allowing to investigate different physics topics. The Micro-Vertex Detector (MVD), which represents the innermost part of the central tracking system, features good spatial resolution, limited material budget, radiation hardness and PID capability. To cope with this requirements the MVD is composed by pixel and strip detectors. The custom pixel detector design foresees thin epitaxial sensors and a readout electronics developed in 130nm CMOS technology able to work in a triggerless environment. The first single chip assembly prototype for the pixel detector of PANDA is composed of the ToPix3 readout chip and a dedicated epitaxial silicon sensor matching in size the 640 readout channel matrix of the ASIC prototype. The bump bonding connection was done by IZM company. To perform the first beam test, a pixel tracking station composed by 4 planes was assembled and tested with 2.7GeV/c protons at Forschungszentrum J¨ulich. The data analysis is presented

Usefulness of transesophageal echocardiography in the assessment of aortic dissection

The acute dissection of the ascending aorta requires prompt and reliable diagnosis to reduce the high risk of mortality; in addition, prognosis is influenced by longterm complications. The aim of this article is to discuss transesophageal echocardiography (TEE) and (1) its diagnostic accuracy in the presurgical evaluation of patients, (2) its role in reducing time of diagnosis and surgery, and (3) its ability to reduce hospital mortality. TEE has also been tested as a screening method in the postsurgical follow-up of these patients. The retrospective investigation concerns a sample of 80 cases of acute dissection of the aorta, submitted for surgical intervention from April 1986 to February 1999. TEE has allowed a precise estimation of aortic diameters and optimal visualization of intimal flap and tear entry with a fine distinction between true and false lumen. A direct comparison of the results of TEE and of transthoracic echocardiography has demonstrated that some elements (visualization of flap and diameters in descending aorta, sites of entry and reentry, direction of let trough intimal tears, phasic intimal flap movement, diastolic collapse of flap on the valvular plane, false lumen thrombosis, coronary involvement, intramural hematoma, and aortic fissuration) were identified only by TEE, whereas other additional diagnostic elements (cardiac tamponade, aortic valve insufficiency, left ventricular function) show a similar pattern of significance. Routine employment of this method has confirmed a reduction of hospitalization time (about 1.5 hours of waiting time), and hospital mortality has changed from 42.8% to 17.3%. In the follow-up of patients operated on for aortic dissection, fundamental information may be obtained from TEE (assessment of the progression of thrombosis in the false lumen with its complete obliteration and modifications in aortic diameter with a consequent, possible worsening of aortic valve insufficiency). In conclusion, our study demonstrated that TEE may provide fast and efficient detection of acute aortic dissection. In the postsurgical follow-up, TEE has confirmed detection of major complications that can influence long-term prognosis and may be proposed as a method with easy access-one that is repeatable and inexpensive for the screening of aortic dissection surgical patients. (C) 2000 by Excerpta Medica, Inc

Performance of the readout system of the ALICE Zero Degree Calorimeters in LHC Run 3

The ALICE Zero Degree Calorimeters (ZDC) provide information about event geometry in heavy-ion collisions through the detection of spectator nucleons and allow to estimate the delivered luminosity. They are also very useful in p–A collisions, allowing an unbiased estimation of collision centrality. The Run 3 operating conditions will involve a tenfold increase in instantaneous luminosity in heavy-ion collisions, with event rates that, taking into account the different processes, could reach 5 MHz in the ZDCs. The challenges posed by this demanding environment lead to a redesign of the readout system and to the transition to a continuous acquisition. The new system is based on 12 bit, 1 Gsps FMC digitizers that will continuously sample the 26 ZDC channels. Triggering, pedestal estimation and luminosity measurements will be performed on FPGA directly connected to the front-end. The new readout system and the performances foreseen in Run 3 are presented

Recent Developments on the Silicon Drift Detector readout scheme for the ALICE Inner Tracking System

Proposal of abstract for LEB99, Snowmass, Colorado, 20-24 September 1999Recent developments of the Silicon Drift Detector (SDD) readout system for the ALICE Experiment are presented. The foreseen readout system is based on 2 main units. The first unit consists of a low noise preamplifier, an analog memory which continuously samples the amplifier output, an A/D converter and a digital memory. When the trigger signal validates the analog data, the ADCs convert the samples into a digital form and store them into the digital memory. The second unit performs the zero suppression/data compression operations. In this paper the status of the design is presented, together with the test results of the A/D converter, the multi-event buffer and the compression unit prototype.Summary:In the Inner Tracker System (ITS) of the ALICE experiment the third and the fourth layer of the detectors are SDDs. These detectors provide the measurement of both the energy deposition and the bi-dimensional position of the track. In terms of readout an SDD can be viewed as a matrix, where the rows are the detector anodes and the columns are the samples to be read during the drift time; therefore, a very large amount of data has to be amplified, converted in digital form and preprocessed in order to avoid the storage of non-significatn data.Since the electron mobility is a strong temperature function, detector temperature has to be kept constant; on the other hand, it is not possible to use very efficient cooling systems because the amount of material in this area is very limited, so the power budget for the electronic readout is very low (less than 6 mW/anode).The simplest solution would be to send the analog signals outside the sensitive area immediately after a preamplification; unfortunately, the ratio between the number of channels (around 200 000) and the space available is so high that the simple solution of sending all the SDD anodes output outside teh detector zone after a low-noise amplification is not practically manageable.Abstract:The adopted solution is based on three main units:(i) A front-end chip that performs low noise amplification, fast analog storage and A/D conversion(ii) A multi-event digital buffer for data derandomization(iii) A data compression/zero suppression and system control boardThe first two units are distributed on the ladders near the detectors and have stringent power and space requirements, while the third unit is placed at both ends of the ladders and in boxes placed on both ends of the TPC detector.The first unit is the most critical part of the system. It works as follows: the detector signals are continuously amplified, sampled and stored in the analog memory with a frequency of 40 MSamples/s The L0d trigger signal stops the write operation, while the L1 trigger signal starts the conversion phase. This phase will continue until the event data are stored in the event buffer if the L2y confirm trigger signal is received, or rejected if the L2n abort signal will be issued by the trigger system.Prototypes of the three parts have been designed and tested while the full chip is currently under design. Tests of the A/D converter will be presented.The multi-event buffer purpose is to de-randomize the even data in order to reduce the transmission speed. Preliminary tests of the first prototype will be presented.The board placed at the end of the ladders performs various functions. It reduces the amount of data through various cascaded algorithms with variable parameters and transmits the data to the SIU board. It also controls the test and slow control system for the ladder circuitry. Tests of the FPGA-based prototypes will be presented.Special care has been taken for the test problem. The ASICs designed are provided of a test control port based on teh IEEE 1149.1 JTAG standard. The same protocol is used for downloading configuration information

Test and commissioning of the CARLOS control boards for the ALICE Silicon Drift Detectors

This paper presents the test strategy employed during the installation of the CARLOS end ladder boards developed for the Silicon Drift Detectors (SDD) of ALICE. Each CARLOS board compresses the data provided by the front-end electronics of one SDD and sends them via an optical link of 800 Mbit/s to the data concentrator card (CARLOSrx) located in the counting room. The paper describes the integration of the CARLOS boards in the final SDD system, including its cooling and mechanical support, the power supply distribution and the optical interconnections. The results of the tests performed after each step of the installation sequence are reported