Exploring the impact of the “Mountain Product” label guarantee on the attitude-intention path

This study aims at verifying a structural model in which the Mountain Product label’s guarantee impacts as a second order construct on the attitude-intention path, considering the intention to purchase mountain food products as dependent variable and controlling for the level of the MP label knowledge. The MP label guarantee acts as a multidimensional construct. All the postulated HPs are verified evidencing the importance played by the MP label guarantee in generating positive attitudes and behavioural intentions in consumers. This can be amplified through a higher product label knowledge. Marketing implications are derived

Daily deal shoppers: What drives social couponing?

This paper contributes to the service marketing literature with a focus on deal-of-the-day (DoD) website shopping. The work explores drivers of adoption of DoD shopping among young consumers. We show that value conscious consumers are less oriented towards DoD while deal-prone consumers are more likely to purchase DoD. In contrast to previous research, which found that price savings are the main reason for coupon use, our study finds that Enjoyment plays a major role in young consumers\u2019 DoD shopping behaviour. DoD platforms could leverage Enjoyment to create a compelling value proposition for both consumer and merchant attraction and retention

Shopping online using the mobile channel: drivers of buying behaviour for Chinese consumers

The emergence of online channels is opening up to new research topics in the retailing literature. Particularly in China, the multifunctional mobile retailing apps, allowing to buy online and socialize the shopping activity with relatives, friends and followers, are supporting the spread of online shopping. A structural equation model combining both traditional antecedents of online shopping - such as ease of use, time convenience, perceived risk - with emerging drivers like perceived price differentiation and shopping socialization is tested to measure the intention to buy using a smartphone by Chinese people. Empirical findings offer new insights for both scholars and practitioners

Exploring how to use virtual tours to create an interactive customer remote experience

This paper investigates the use of Virtual Reality (VR) to develop virtual tour applications for marketing purposes. The aim is to explore how virtual technologies can support the creation of knowledge about a specific food product and the achievement of user engagement by a multi-sensory virtual tour of the real production site. The study provides design guidelines to create a valuable, multisensory experience by VR tours and demonstrate how the adoption of a user-driven approach, instead of a technology-driven approach, allows to achieve a positive intention to buy. The case study was represented by one of the excellences among Italian food products, the Parmigiano Reggiano (PR) cheese. The PR virtual tour was validated by a user testing campaign, involving more than 70 users: users' reactions and feedback were collected by human physiological data monitoring and questionnaires' administration. The research results demonstrated how virtual technologies could effectively help people to create a solid knowledge about a food product to support the marketing process and to form an intention to buy thanks to a better understanding of the quality of the local and traditional productions

Capacità dinamiche e vantaggio competitivo: un’analisi empirica nel retail

Obiettivi. L’articolo studia il tema delle capacità dinamiche nel retail, verificando l’impatto delle sue componenti sulle performance competitive di un campione di piccoli imprenditori commerciali al dettaglio. Metodologia. La ricerca è stata svolta somministrando un questionario strutturato ad un campione di imprenditori commerciali al dettaglio. I dati raccolti sono stati elaborati applicando una regressione lineare multipla. Risultati. Le evidenze empiriche mostrano come la creazione di conoscenza e di integrazione della stessa impattano in modo significativo e positivo sulle performance competitive, mentre capacità dinamiche legate a processi strutturati di apprendimento e riconfigurazione delle risorse agiscono in senso opposto. Limiti della ricerca. L’articolo esplora come le capacità dinamiche impattano sulle performance di piccoli imprenditori industriali al dettaglio; l’originalità dell’analisi e i pochi studi empirici di riferimento circoscrivono la lettura degli effetti evidenziati, che richiedono ulteriori approfondimenti. Implicazioni pratiche. I piccoli imprenditori commerciali al dettaglio in sede fissa dovrebbero puntare sulla capacità di innovare la propria offerta, rivedendola sia in termini di assortimento offerto che di servizio erogato, migliorando la capacità di alimentare un network con i propri stakeholder, fornitori e clienti in primis. Originalità del lavoro. Ad oggi la letteratura di retail ha scarsamente investigato il tema delle capacità dinamiche, rari sono gli studi empirici sul tema e limitati ad indagini di tipo qualitativo con finalità sostanzialmente esplorative. Il paper intende contribuire a colmare tali gap con una ricerca originale, sulla base di una raccolta dati ad hoc

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 7 64 pixels with 50 \ub5m 7 50 \ub5m pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 \ub5m 7 50 \ub5m and single readout electrode 25 \ub5m 7 100 \ub5m 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre- and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Pixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. This paper describes the program of development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The RD53 collaboration effort is described together with the CHIPIX65 INFN project