Production and test of a readout chip for the ALICE SDD experiment

The paper summarizes the design, the fabrication and test of a chip for the silicon drift detector experiment, part of the A Large Ion Collider Experiment (ALICE) at CERN. The chip performs data reduction via bidimensional compression and packing for the readout chain of the experiment. The chip interfaces with front-end electronics and with the counting room. It is synchronized with a 40 MHz system master clock and configured via a serial signal. The work presents the tests that were performed to characterize the chip and it exploits the final yield of 89% over 700 fabricated chips. The whole tests were performed in laboratory and the chip was also tested in a test beam at CERN in November 2004

General purpose readout board {\pi} LUP: overview and results

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the $\pi$LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7$^{th}$-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5$\,$Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of $\pi$LUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS Student Paper Award Second Prize

Design of Very High Speed CMOS Fuzzy Processors for Applications in High Energy Physics Experiments

Abstract We faced the problem of VLS

Test and commissioning of the CARLOS control boards for the ALICE Silicon Drift Detectors

This paper presents the test strategy employed during the installation of the CARLOS end ladder boards developed for the Silicon Drift Detectors (SDD) of ALICE. Each CARLOS board compresses the data provided by the front-end electronics of one SDD and sends them via an optical link of 800 Mbit/s to the data concentrator card (CARLOSrx) located in the counting room. The paper describes the integration of the CARLOS boards in the final SDD system, including its cooling and mechanical support, the power supply distribution and the optical interconnections. The results of the tests performed after each step of the installation sequence are reported

DRM2: the readout board for the ALICE TOF upgrade

For the upgrade of the ALICE TOF electronics, we have designed a new version of the readout board, named DRM2, a card able to read the data coming from the TDC Readout Module boards via VME. A Microsemi Igloo2 FPGA acts as the VME master and interfaces the GBTx link for transmitting data and receiving triggers and a low-jitter clock. Compared to the old board, the DRM2 is able to cope with faster trigger rates and provides a larger data bandwidth towards the DAQ. The results of the measurements on the received clock jitter and data transmission performances in a full crate are given

Radiation tests and production test strategy for the ALICE TOF readout upgrade board

The readout board for the ALICE TOF detector named DRM2 is now in the production phase: 88 boards are being produced (72 are needed in the experiment). Since the boardwill operate in a radiation environment (0.13 krad total dose expected in 10 years and a flux of 0.26 KHz/cm$^2$ of hadrons with energy above 20 MeV), a complete irradiation campaign at the component level was performed. In this paper the focus is on the irradiation tests on a Microsemi Igloo2 FPGA and two different types of Avago SFP optical transceivers using a 100 MeV proton beam, available at the facility operated byINFN-TIFPA at the Centro di Protonterapia in Trento. This paper also focuses on the board production test strategy

Test of the end-ladder prototype board of the ALICE SDD experiment

The paper presents an end-ladder card prototype of the data acquisition chain of the ALICE SDD experiment. The prototype includes most of the electronics devices that will be applied to ALICE SDD experiment. The card interfaces with the front-end electronics and with the counting room detector data link via the interface card named CARLOS_rx. The end_ladder PCB has been fully tested by providing control signals and input vectors via a pattern generator and by collecting output data via the detector data link