Local times and Tanaka--Meyer formulae for c\`adl\`ag paths

Three concepts of local times for deterministic c{\`a}dl{\`a}g paths are developed and the corresponding pathwise Tanaka--Meyer formulae are provided. For semimartingales, it is shown that their sample paths a.s. satisfy all three pathwise definitions of local times and that all coincide with the classical semimartingale local time. In particular, this demonstrates that each definition constitutes a legit pathwise counterpart of probabilistic local times. The last pathwise construction presented in the paper expresses local times in terms of normalized numbers of interval crossings and does not depend on the choice of the sequence of grids. This is a new result also for c{\`a}dl{\`a}g semimartingales, which may be related to previous results of Nicole El~Karoui and Marc Lemieux

GORA: Goodput Optimal Rate Adaptation for 802.11 using Medium Status Estimation,”

Abstract-Rate Adaptation for 802.11 has been deeply investigated in the past, but the problem of achieving optimal Rate Adaptation with respect not only to channel-related errors but also to contention-related issues (i.e., collisions and variations in medium access times) is still unsolved. In this paper we address this issue by proposing 1) a practical definition of the Medium Status in a multi-user 802.11 scenario in terms of channel errors, MAC collisions and packet service times, and a method for its estimation based on measurements; 2) an analytical model of the goodput performance as a function of the Medium Status; 3) a rate adaptation algorithm, called Goodput Optimal Rate Adaptation (GORA), which is based on this model. Unlike other Rate Adaptation schemes proposed in literature, which require either modifications to the IEEE 802.11 standard or cooperation among nodes, GORA is totally stand-alone and standard compliant. In fact, the Medium Status Estimation used by GORA is obtained by using standard MAC counters that are commonly collected by commercial MAC drivers, and no explicit interactions with the other devices in the network is required. Therefore, GORA offers the advantage of being readily deployable on real devices. The performance of GORA is evaluated through NS2 simulations which reveal that, as expected, GORA outperforms other wellknown Rate Adaptation algorithms in several scenarios and can be used as a new reference benchmark

Accelerating Binary and Mixed-Precision NNs Inference on STMicroelectronics Embedded NPU with Digital In-Memory-Computing

The proliferation of embedded Neural Processing Units (NPUs) is enabling the adoption of Tiny Machine Learning for numerous cognitive computing applications on the edge, where maximizing energy efficiency is key. To overcome the limitations of traditional Von Neumann architectures, novel designs based on computational memories are arising. STMicroelectronics is developing an experimental low-power NPU that integrates Digital In-Memory Computing (DIMC) SRAM with a modular dataflow inference engine, capable of accelerating a wide range of DNNs. In this work, we present a 40nm preliminary version of this architecture with DIMC-SRAM tiles capable of in-memory binary computations to dramatically increase the computational efficiency of binary layers. We performed power/performance analysis to demonstrate the advantages of this paradigm, which in our experiments achieved a TOPS/W efficiency up to 40x higher than traditional NPU implementations. We have then extended the ST Neural compilation toolchain to automatically map binary and mixed-precision NNs on the NPU, applying high-level optimizations and binding the models’ binary GEMM and CONV layers to the DIMC tiles. The overall system was validated by developing three real-time applications that represent potential real-world power-constrained use-cases: Fan spinning anomaly detection, Keyword spotting and Face Presence Detection. The applications ran with a latency < 3 ms, and the DIMC subsystem achieved a peak efficiency > 100 TOPS/W for binary in-memory computation