Ultra low power adiabatic logic using diode connected DC biased PFAL logic

With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic), 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic), and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family

Ultra low power high speed domino logic circuit by using FinFET technology

Scaling of the MOSFET face greater challenge by extreme power density due to leakage current in ultra deep sub-micron (UDSM) technology. To overcome from this situation double gate device like FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gate, which mitigate shorter channel effect and exponentially reduces the leakage current. In this research paper utilize the property of FinFET in domino logic, for high speed operation and reduction of power consumption in wide fan-in OR gate. Proposed circuit is simulated in FinFET technology by BISM4 model using HSPICE at 32nm process technology at 250C with CL=1pF at 100MHz frequency. For 8 and 16 input OR gate we save average power 11.5%,11.39% in SFLD, 22.97%, 18.12% in HSD, 30.90%, 34.57% in CKD in SG mode and for LP mode 11.26%, 15.78% in SFLD, 19.74%, 17.94% in HSD, 45.23%, 34.69% in CKD respectivel