Impact of surface treatment under the gate on the current collapse of unpassivated AlGaN/GaN heterostructure field-effect transistors

Unpassivated GaN/AlGaN/GaN/SiC heterostructure field-effect transistors were fabricated on intentionally undoped and 5 x 10(18) cm(-3) modulation-doped material structures. The influence of surface treatment before gate metallization on the gate leakage and drain current collapse of the devices was observed. In the case of a short HCl treatment (similar to 5 s), a relatively small gate leakage ( 10(-4) A mm(-1)) and a simultaneously negligible current collapse (< 5%). This effect is qualitatively similar in devices prepared on the undoped and doped heterostructures. It is assumed that a thin interfacial oxide layer under the gate might be responsible for a lower leakage current and a larger current collapse of the devices

Tuning III-nitride nano-LEDs via laser-micro-annealing

Conventional reactive ion etching (RIE) used for the space definition/formation of nano-LEDs leads to a significant decrease in their electroluminescence. Among all the technological approaches to boost the efficiency of micrometer and nano- sized LED structures, the precise local laser micro annealing (LMA) procedure exhibits still undiscovered potential. The main goal behind the application of the “LMA” procedure is to “adjust” and/or to “engineer” the emission intensity of nano-LEDs according to requirements for example in transmistor based optical computing architectures currently under development. Here in this work, we present correlative ̶ optical (micro electro- & photoluminescence, Raman spectroscopy) and electrical ̶ characterization of single nano-LEDs in arrays integrated into a vertical device layout. Scanning electron microscopy investigations (figure 1) reveal inhomogeneous surface nano-LED morphology. Micro photoluminescence studies indicate that the LMA process has a direct impact on the curing of etching related defects. These are responsible for the suppression of radiative recombination in the nano-LED devices. Figure 2 presents a micro electroluminescence mapping after the successful “conditioning” procedure performed on nano-LEDs in an array with different annealing conditions. Furthermore, micro-Raman thermography investigations performed on single nano-LED structures (after LMA) disclose an up to 60K decrease in work temperature. Additionally, long-term operation electroluminescence measurements (up to 5000 hours) indicate that the LMA approach affects the nano-LEDs performance as well as device lifetime and reliability advantageously. The results presented demonstrate the suitability and reliability of the vertically integrated nano-LEDs conditioned locally/selectively by LMA as a key component for future on chip integrated electro-optic convertors. They could play an important role in the development of novel optical computing architectures based on transmistor/all optical switch units. Figure 1: Scanning electron micrograph of a single nano-LED structure with its nickel cap (serving as the etching mask) after the RIE process. The “base” region of the nano-LED exhibits a “shallower” chemical/physical corrosion depth. Figure 2: micro electroluminescence map-ping, after the “conditioning” procedure, performed on nano-LEDs in an array with different annealing conditions: non-locally annealed E0 and locally E1 and E2 annealed

Defect states characterization of non-annealed and annealed ZrO2/InAlN/GaN structures by capacitance measurements

InAlN/GaN metal-oxide-semiconductor structures with non-annealed and annealed ZrO2 gate insulators were characterized by capacitance-voltage (C-V) measurements. A significant capacitance hysteresis in both channel depletion and barrier accumulation regions was observed on the non-annealed structures. Fixed positive charge in the gate insulator was identified from the negative shift of the C-V curves. The C-V hysteresis was negligible and the threshold voltage decreased with a corresponding increase of the sheet charge density by 6 x 10(12) cm(-2) after annealing. The C-V slope in the accumulation region increased and the flat-band voltage decreased with decreased frequency. This confirms a decrease of the oxide/barrier interface trap state density with increased their activation energy. Capacitance saturation in the accumulation region occurs at lower values than it is in the insulator capacitance. Measurements at increased temperature up to 150 degrees C show a shift of the flat-band voltage to lower values. Both facts support an explanation that leakage current through the gate insulator occurs in the barrier accumulation region. This shows that evaluation of the trap states density from this part of the C-V curves might be difficult. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4792060

Degradation of AlGaN/GaN high-electron mobility transistors in the current-controlled off-state breakdown

We investigate degradation mechanisms in AlGaN/GaN HEMTs which were repeatedly driven into the current-controlled off-state breakdown or subject to 60 s voltage- or current-controlled off state stresses. The current-controlled sweep in to the breakdown allows the sustainability of breakdown that can not be observed in the voltage controlled sweep. Only temporal changes were observed in the HEMT dc performance after repetitive sweeps, which were explained by charging/discharging of the HEMT surface at the gate-to-drain access region and in the GaN buffer below the gate. Similar changes were observed also if high-voltage stress has been applied on the drain; however, permanent degradation appears after 60 s current-controlled breakdown stress. In this case, the drain leakage current, as well as the breakdown current, increases significantly. On the other hand, the breakdown voltage, as well as the gate characteristics, remains unaltered. We suggest that the avalanche-injection process is governing the off-state breakdown event with a dominant role of the potential barrier at the channel-buffer interface. (C) 2014 AIP Publishing LLC

Oxidized Al Film as an Insulation Layer in AlGaN/GaN Metal-Oxide-Semiconductor Heterostructure Field Effect Transistors

We report on the technology of a very thin oxidized Al sputtered film used for gate insulation and passivation in Al2O3/AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs). Their transport properties are presented. The MOSHFET with the Al2O3 layer had improved static output and transfer characteristics compared with the reference heterostructure field-effect transistors (HFETs): (1) their saturation drain current I-DS was similar to 600 mA mm(-1) at gate voltage V-G = 1 V (HFETs with 2.5 mu m gates had similar to 430 mA mm(-1)); (2) their transconductance was 116-140 mS mm(-1) (HFETs had similar to 70 mS mm(-1)). (C) 2010 The Japan Society of Applied Physic

Novel Douple-Level-T-Gate tecnology

We developed a novel double-level-T-gate technology based on wet etching of a metal gate interlayer. With the help of this technological process we prepared T-gate feet with widths as small as 200 nm. The major advantage of our process is its use of only standard optical lithography. It allows the fabrication of 100 nanometer size T-gates for transistors. High electron mobility transistors (HEMTs) were fabricated on an AlGaN/GaN/sapphire material structure with an original gate length Lg of 2 µm. Their cutoff frequency of 6 GHz was improved to 60 GHz by etching the gate to a 200 nm length double T-gate contact