Design of isofrequency reconfigurable repeaters

The advances in the communications systems has brought new requirements and challenges in terms of compactness and efficient systems that looking for increase the signal coverage area. The reconfigurable antennas are a promising solution for the communication systems when looking to improve the channel capacity and/or to extend the signal coverage. The main advantages of the reconfigurable antennas are the capabilities to change their frequency, polarization and radiation beam steering at a low cost. The reconfigurable antennas can be designed to operate in a determined changing environment keeping good electromagnetic characteristics. The design of reconfigurable RF repeaters is a relevant application of this reconfigurable antenna principle. This thesis is devoted to study and propose new repeater architectures in which a set of reconfigurable parasitic elements as part of the repeater are used for reducing the electromagnetic coupling between the Rx and Tx antennas. It is shown that the use of the parasitic elements as a reconfigurable mechanism gives the flexibility to adapt the repeater electromagnetic characteristics to changing environments while keeping a good system performance. The determination of the minimum number of parasitic elements is an important parameter and it is determined by a modal analysis to define the minimum number of parasitic elements able to fulfill specific repeater electromagnetic characteristics. In order to validate the analytical results, different reconfigurable repeater prototypes controlled electronically are manufactured. A reconfigurable repeater prototype that is using eight reconfigurable parasitic elements has been designed for operating at different scatterer environments. The repeater reconfigurable capabilities are studied to evaluate the repeater performance in realistic indoor locations. Finally, in order to obtain a repeater with reconfigurable frequency isolation capabilities between the Rx and Tx antennas over a wide frequency range, a repeater prototype based on a pixeled layer as reconfigurable mechanism has been designed and measured

VLSI implementation of a transconductance mode continuous BAM with on chip learning and dynamic analog memory

In this paper we present a complete VLSI Continuous-Time Bidirectional Associative Memory (BAM). The short term memory (STM) section is implemented using small transconductance four quadrant multipliers, and capacitors for the integrators. The long term memory (LTM) is built using an additional multiplier that uses locally available signals to perform Hebbian learning. The value of the learned weight is present at a capacitor for each synapse. After learning has been accomplished the value of the stored weight voltage can be refreshed using a simple AID-D/A conversion, which if done fast enough, will maintain the weight value within a discrete interval of the complete weight range. Such a discretization still allows good performance of the STM section after learning is finished

Analog integrated neural-like circuits for nonlinear programming

A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques is presented. The method is based on formulating a dynamic gradient system whose state evolves in time towards the solution point of the corresponding programming problem. A neuron cell for the linear and the quadratic problem suitable for monolithic implementation is introduced. The design of this neuron and its corresponding synapses using SC techniques is considered in detail. An SC circuit architecture based on a reduced set of basic building blocks with high modularity is presented. Simulation results using a mixed-mode simulator (DIANA) and experimental results from breadboard prototypes are included, illustrating the validity of the proposed technique

Analog Neural Programmable Optimizers in CMOS VLSI Technologies

A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind of problem in MOS VLSI. This architecture is a fully programmable and reconfigurable one exploiting SC techniques for the analog part and making extensive use of digital techniques for programmability

On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's

A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA and this makes the reported structures well-suited for building voltage controlled oscillators (VCO's). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented which are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes are included showing good potential of OTA-based oscillators for high frequency VCO operation.Comisión Interministerial de Ciencia y Tecnología ME87-000

CMOS OTA-C high-frequency sinusoidal oscillators

Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the CMOS OTA's dominant nonidealities. Building blocks are presented for amplitude control, both by automatic gain control (AGC) schemes and by limitation schemes. Experimental results from 3- and 2- mu m CMOS (MOSIS) prototypes that exhibit oscillation frequencies of up to 69 MHz are obtained. The amplitudes can be adjusted between 1 V peak to peak and 100 mV peak to peak. Total harmonic distortions from 2.8% down to 0.2% have been measured experimentally.Comisión Interministerial de Ciencia y Tecnología ME87-000

Frequency tuning loop for VCOs

A frequency tuning circuit is introduced for VCOs (voltage-controlled oscillators) so that the final relationship between oscillating frequency and input control voltage is fixed and independent of nonidealities. This tuning loop is applied to an OTA-C sinusoidal VCO. Such an oscillator has an output frequency-input voltage relationship that depends on temperature, process parameters, and even amplitude of the oscillations. It is shown that, by adding the tuning loop, nonideal dependences will be minimized