Interference of Periodic and Spread-Spectrum-Modulated Waveforms with Analog and Digital Communications

In this article, the effectiveness and the limitations of spread-spectrum (SS) modulation techniques employed in switching-mode power converters and in digital systems to mitigate interference with communication equipment are analyzed and discussed under the EMC standard perspective and under an information theoretical perspective, with reference to different real-world scenarios. Substantial difference between potential EMI issues in traditional analog radio/TV broadcasting, digital data lines, and digital links featuring advanced channel coding techniques, e.g. in emerging power line communication (PLC) systems, are highlighted. Practical recommendations on the adoption of SS modulations along with a general reflection on the evolution of EMC requirements are finally given

Interference of Spread-Spectrum Switching-Mode Power Converters and Low-Frequency Digital Lines

The interference between switching mode power converters and wireline digital communications is addressed in this paper and the impact on communication errors of different Spread Spectrum (SS) modulation techniques, which are commonly used in power convertors to comply with EMC regulations, is experimentally investigated in a particular case. Experimental results do not highlight significant differences in terms of communication error rate induced in the victim data line between power converters featuring conventional and SS pulse width modulations

FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514,S/s prototype (ReDAC1) and on a 11-bit, 10.5,kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68,LSB (1.53,LSB) maximum INL, 1.54,LSB (1.0,LSB) maximum DNL, 76.4,dB (67.9,dB) THD, 79.7,dB (71.4,dB) SFDR and 71.3,dB (63.3,dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB)

Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000um^2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications. (PDF) Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS. Available from: https://www.researchgate.net/publication/336552301_Design_of_Relaxation_Digital-to-Analog_Converters_for_Internet_of_Things_Applications_in_40nm_CMOS [accessed Nov 16 2019]

A Sub-Leakage pW-Power Hz-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply

A pW-power versatile relaxation oscillator operating from sub-threshold (0.3V) to nominal voltage (1.8V) is presented, having Hz-range frequency under sub-pF capacitor. The wide voltage and low sensitivity of frequency/absorbed current to the supply allow the suppression of the voltage regulator, and direct powering from harvesters (e.g., solar cell, thermal from machines) or 1.2-1.5V batteries. A 180nm testchip exhibits a frequency of 4 Hz , 10%/V supply sensitivity at 0.3-1.8V, 8-18pA current, 4%/°C thermal drift from -20°C to 40°C

Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3V

A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed circuit is fully synthesizable, as it can be designed with automated digital design flows and standard cells, and can operate at very low voltages down to deep sub-threshold. Post-layout simulations show correct operation for rail-to-rail common-mode inputs at a supply voltage VDD down to 0.3 V. At such voltage, the input offset voltage standard deviation is less than 28 mV (8 mV) over the rail-to-rail common-mode input range (around VDD/2). The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain. The ease of design, the low area and the voltage scalability make the proposed comparator very well suited for sensor nodes, integrated circuits for the Internet of Things and related applications

Suppression of Quantization-Induced Limit Cyclesin Digitally Controlled DC-DC Converters by Dyadic Digital Pulse Width Modulation

Quantization-induced limit cycle oscillations (LCOs) in digitally controlled DC-DC converters are addressed in this paper. The novel Dyadic Digital PWM (DDPWM) is proposed to increase the effective pulse-width-modulator (PWM) resolution, as required for LCO free operation, at low cost, without sacrificing DC accuracy and with no detrimental effects on the ripple voltage. Experimental results on a synchronous buck validate the approach highlighting effective LCOs suppression and DC accuracy enhancement at 5x reduced output voltage ripple compared to thermometric dithering for the same resolution increase

Effects of the Switching Frequency of Random Modulated Power Converter on the G3 Power Line Communication System

Power Line Communication (PLC) technologies utilize existing power cables for both power and data transmission which minimizes cost and complexity. However, recent studies show that alternative modulation schemes such as Random Pulse Width Modulation (RPWM), applied to power converter to minimize conducted emissions, have possible side effects on the PLC system. In this work, the effects of the switching frequency of randomly modulated power converter on the G3-PLC system is investigated. To this end, a range of switching frequencies from 10 kHz-100 kHz is applied to a randomly modulated DC-DC converter and its potential effect on the G3-PLC is studied. Experimental results confirmed that switching frequencies near the bandwidth of the G3-PLC caused significant disturbance and possible coexistence issue compared to the frequencies out of this range. Moreover, there is a tradeoff between Electromagnetic Interference (EMI) reduction and coexistence issue that is Random Frequency Modulation, which is very effective for EMI reduction, is found to be very disruptive for G3-PLC, compared to alternative random modulation techniques like Random Pulse Position Modulation