A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000um^2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications. (PDF) Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS. Available from: https://www.researchgate.net/publication/336552301_Design_of_Relaxation_Digital-to-Analog_Converters_for_Internet_of_Things_Applications_in_40nm_CMOS [accessed Nov 16 2019]

Aiello, Orazio

Crovetti, Paolo S.

Rubino, Roberto

English

A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000μm2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications

Rubino R.

Crovetti P. S.

Aiello O.

Archivio istituzionale della ricerca - Università di Genova

Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

Roberto Rubino

Paolo S. Crovetti

Orazio Aiello

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

04 August 2020POLITECNICO DI TORINORepository ISTITUZIONALEDesign of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS / Rubino, Roberto;Crovetti, Paolo S.; Aiello, Orazio. - ELETTRONICO. - (2019). ((Intervento presentato al convegno APCCAS 2019 - 2019IEEE Asia Pacific Conference on Circuits and Systems tenutosi a Bangkok (TH) nel Nov. 11-14 2019.OriginalDesign of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOSieeePublisher:PublishedDOI:Terms of use:openAccessPublisher copyrightcopyright 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all otheruses, in any current or future media, including reprinting/republishing this material for advertising or promotionalpurposes, creating .(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2767652 since: 2019-11-16T14:43:04ZIEEEDesign of Relaxation Digital-to-Analog Convertersfor Internet of Things Applications in 40nm CMOSRoberto Rubino1, Paolo S. Crovetti1 and Orazio Aiello1,21Dipartimento di Elettronica e Telecomunicazioni (DET), Politecnico di Torino, Torino, Italy2Department of Electrical and Computer Engineering, National University of Singapore, Singapore{roberto.rubino,paolo.crovetti,orazio.aiello}@polito.itAbstract—A 10-bit-400kS/s and a 10-bit-2MS/s RelaxationDigital to Analog Converters (ReDAC) in 40nm are presentedin this paper. The two ReDACs operate from a 600mV powersupply, occupy a silicon area of less than 1,000µm2. Thefirst/second DAC achieve a maximum INL of 0.33/0.72 LSB anda maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based onpost-layout simulations. The average energy per conversion is lessthan 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv.step), which make them well suited to Internet of Things (IoT)applications.Index Terms—Relaxation Digital to Analog Converter(ReDAC), Digital to Analog Converter (DAC), Fully SynthesizableDAC, Ultra Low Power, Internet of Things.I. INTRODUCTIONTraditional analog design techniques are generally unsuit-able to address the tight requirements of ultra-low power,ultra-low voltage operation, low cost and design effort ofinterfaces for Internet of Things (IoT) applications and mostlydigital solutions and IC design approaches suitable to replaceconventional analog and mixed signal circuits are thereforeintensely investigated in the last years [1-2].Focusing on digital-to-analog converters (DACs), which arekey building blocks in themselves and also as part of analog-to-digital converters (ADCs), topologies based on weighted ca-pacitors arrays [3-5] are in general extremely energy efficientbut can be sensitive to parasitics and have in general stringentmatching requirements, which may result in increased totalcapacitance (with a penalty in energy and area), design timeand layout effort. An analog intensive design is also requiredfor multi-bit sigma-delta (Σ∆) DACs [6], while single Σ∆and dyadic DACs are fully digital and matching insensitive,but operate either at high clock frequencies or require largepassive components unsuitable to integration [7-8].Recently, the Relaxation Digital to Analog Converter(ReDAC) has been proposed in [10] as a low-cost alternativefor bitstream data conversion in ultra-low voltage, tightly en-ergy constrained IoT applications and has been demonstratedby a field-programmable gate array (FPGA) proof-of-conceptprototype.In this paper, the design of two fully synthesizable ReDACsin 40nm CMOS is discussed and their performance is demon-strated by post-layout simulations. The paper has the followingThis project has received funding from the European Union’s Horizon 2020research and innovation programme under the Marie Skłodowska-Curie grantagreement No 703988 (ULPIoT project).Digital Control Unitfully synthesizableReDAC corefully synthesizablep-cells baseddesignMoMhi-respolypassivesdigital inputfrom testing harnessfrom testingharnessDATA INFig. 1. Relaxation DAC Block Diagram (a) and principle of operation (b)structure: the principles and main features of ReDACs arerevised in Sect.II. Then, in Sect.III, the design of the convertersis addressed focusing on the tradeoffs and on the optimizationof passives to obtain the best energy-accuracy tradeoff. InSect.IV, the performance of the ReDACs is discussed based onpost-layout simulations. Finally, in Sect.VI, some conclusionsare drawn.II. RELAXATION DIGITAL-TO-ANALOG CONVERSIONCONCEPT AND FEATURESThe ReDACs proposed in this paper exploit the impulseresponse of an RC network as a mean to generate binaryweighted voltages and sum them up according to the digitalinputn =N−1∑i=0bi2i, (1)to be converted. The ReDAC operation principle and its mainfeatures, which have been described in [10], are shortly revisedin what follows.A. Relaxation DAC Operation PrincipleA ReDAC includes a first-order RC network driven by athree-state digital buffer, as depicted in Fig.1a. When enabled,the buffer drives the RC network by a sequence of Nrectangular pulses of the same duration T and amplitudeVDDbi, which is equal to VDD or 0V, depending on the logicalvalue of the N bits bi of the digital input n to be converted,starting from the least significant bit (LSB) b0 up to themost significant bit (MSB) bN−1 as in Fig.1b. This is easilyaccomplished in practice by driving the input of the buffer byan N -bit shift register loaded by the input n to be converted.The operation of the circuit in Fig.1a as a D/A convertercan be explained considering that the evolution of the capacitorvoltage vC(t) during the ith time interval [(i− 1)T, iT ] canbe expressed as a function of the initial capacitor voltage atthe beginning of the interval, i.e. vC,i−1 = vC(t)|t=(i−1)T , ofthe steady-state voltage vC,i(∞), which is VDD for bi = 1 and0V for bi = 0, and of the time constant τ = RC, asvC(t) = vC,i(∞)[1− e− t−(i−1)Tτ]+ vC,i−1e−t−(i−1)Tτ (2)Assuming vC,0 = vC(0) = 0 as a reset condition, (2) canbe iterated to express vC,i for i = 1 . . . N − 1 in function ofVDD, bi and τ and the capacitor voltage after N clock periodscan be finally expressed as:vC(NT ) = VDD(1− e−Tτ)·N−1∑i=0bie− (N−i−1)Tτ . (3)Based on (3), if T is chosen so that:e−Tτ =12=⇒ T = τ log 2 (4)by substituting condition (4) in (3)vC(NT ) =VDD2N·N−1∑i=0bi2i =n2NVDD, (5)i.e., it follows that vC(NT ) is proportional to the binary inputvalue n expressed by (1), as demanded in D/A conversion. Thecapacitor voltage vC(NT ) is finally held constant by releasingthe enable signal of the three-state buffer.B. Relaxation DAC FeaturesBased on the results presented in [10], a ReDAC is partic-ularly appealing for low cost, low power IoT systems. Unlikein binary weighted capacitors array DACs [3-4], in fact, itrequires a single capacitor and its linearity is not affectedby matching. In view of that, a ReDAC can be extremelyarea and energy efficient since the minimum capacitance C isnot constrained neither by matching nor by the minimum unitcapacitance available in the process design kit (PDK).Moreover, the ReDAC linearity depends on the singleprocess-sensitive quantity T/τ and the worst case integralnonlinearity error (INL), expressed in least significant bits(LSBs) has been found to beINLmax ' 2N−1 log 2 · ∆TT(6)Poly resitor parasiticshi-respolyCpar CR/k R/k R/kC+CArea2910�mOverallpar parequivalenttoFig. 2. Poly resistor parasitics and layout of the ReDAC design #1.where ∆T is the error in the clock period T compared to therequirement (4) for ReDAC operation.Since time intervals, unlike voltages, currents and ac-tive/passive component parameters, can be finely controlledand tuned with a high resolution and the value of T requiredto meet condition (4) can be conveniently enforced by thedigital dichotomic calibration procedure presented in [10], aReDAC can easily achieve a resolution exceeding 10 bits andis particularly well suited to IoT applications.III. REDAC DESIGN IN 40NM CMOSThe design of two 10-bit ReDACs in 40nm CMOS targeting400kS/s sample rate and best accuracy (design #1) and 2MS/ssample rate (design #2) is now addressed. Both the ReDACsinclude a digital core, a control unit and an integrated RCnetwork, as in the block diagram of Fig.1a, and are assumedto be operated by a clock signal with a period T calibrated bythe dichotomic procedure presented in [10] so that to enforcecondition (4) (the calibration procedure will not be consideredhereafter). The design of the RC network and of the digitalblocks is discussed in what follows.A. RC Network DesignIn both the ReDACs, the capacitor of the RC networkis implemented by a Metal-oxide-Metal (MoM) capacitoravailable in the PDK. Since there is no matching requirementin a ReDAC converter, a capacitance C close to the limitdictated by thermal noise to keep the 3σ value of the κT/Cnoise below 1/2 LSB, i.e.:Cmin ' 9 · 22N+2κT/V 2DD (7)can be chosen to minimize the silicon area and the energyper conversion. At 10 bit resolution and 0.6V supply voltage,based on Eqn.(7), Cmin = 436fF. A capacitance of C=1pF, i.e.nearly twice Cmin, is therefore chosen in the ReDAC design-1-0.500.510 100 200 300 400 500 600 700 800 900 1000-0.4-0.200.20.4-0.3-0.2-0.10input code, nINL, LSBDesign #2: DNL  = 1.27 LSB - DNL  = 0.07 LSB   max rms0 100 200 300 400 500 700 800 900 10000 100 200 300 400 500 600 700 800 900 1000600input code, ninput code, nDNL, LSBINL, LSB-1.5-1-0.500.50 100 200 300 400 500 600 700 800 900 1000input code, nDNL, LSBDesign #2: INL  = 0.72 LSB - INL  = 0.34 LSB   max rmsDesign #1: DNL  = 0.2 LSB - DNL  = 0.01 LSB   max rmsDesign #1: INL  = 0.33 LSB - INL  = 0.1 LSB   max rmsFig. 3. Integral nonlinearity error (INL) and differential nonlinearity error(DNL) of design #1 and desing #2 obtained by post-layout simulations.0 200 400 600 800 100000.20.40.60.811.21.41.6Total (avg: 0.728pJ)0 200 400 600 800 1000code00.20.40.60.811.21.41.6Energy per Conversion [pJ]Energy per Conversion [pJ]codeDigital BlocksTotal (avg. : 1.10pJ)Digital BlocksDesign #1 Design #2Fig. 4. Energy per conversion versus input code#1 to make the thermal noise contribution negligible, while acapacitance of C=450fF, close to the thermal noise limit, ischosen for ReDAC #2.The resistor R is implemented by high-resistivity (HiRes)polysilicon resistors in the PDK and its resistance value R isdesigned for a target time constant, based on the capacitancevalues C derived above, asR =τC(8)where the target value of τ is related to the bit time T by (4),and is in turn related to the target sample rate of the circuit,beingTconv = (N + 2)T = (N + 2)τ log 2 (9)where N is the number of bits and a 2T hold phase is assumed.Based on (9) and (8), a resistance R = 288kΩ is chosen0 20 40 60 80 100 120 140 160 180 200-120-100-80-60-40-200SFDR = 76.8 dBSNDR = 61.0 dBTHD = 66.7dBENOB = 9.9SFDR  76.8 dBfrequency, [kHz]normalized amplitude [dBFS]normalized amplitude [dBFS]-120-100-80-60-40-200frequency, [kHz]SFDR  62.4 dBSFDR = 62.4 dBSNDR = 58.3 dBTHD = 62.2 dBENOB = 9.40 100 200 300 400 500 600 700 800 900 1000a) Design #1b) Design #2Fig. 5. Spectrum of the DACs output (sampled in the hold phase) and dynamicparameters: a) design #1 at 3.4kHz sine wave input 90% full-swing amplitude;b) design #1 at 16.8kHz sine wave input 90% full-swing amplitude.in design #1 for a 400kS/S sample rate and a resistance ofR = 128kΩ is chosen in design #2 for a 2MS/s sample rate.In practice, two more contrasting requirements need to beconsidered in the choice of R to avoid accuracy degradation.First, R should be much larger than the output impedanceof the buffer in Fig.1a so that to avoid nonlinear loadingeffect; second, the total distributed parasitic capacitance of Rhighlighted in Fig.2 should be negligible compared to C at thetarget resolution (∼ 2N times less) to have a true first-orderRC response, as demanded for the validity of the analysisin Sect.II. Since the absolute value of the resistance is notcritical in a ReDAC and it can be compensated by period Tcalibration [10], the physical width of the poly resistor hasbeen set to the minimum allowed by the PDK to reduce thedistributed capacitance. Moreover, the loading effect and theparasitics have been verified to be negligible for the resistancevalues considered in the design.B. Digital Core and Control Unit DesignThe 10-bit shift register ReDAC core and the control unit fi-nite state machine (FSM), which generates the LOAD/SHIFTand ENABLE signals according to the timing in [10], are bothsynthesized in standard cell logic starting from a behavioralVerilog description. Both the netlist and the layout view havebeen automatically generated in a standard digital flow.The strength of the three-state buffer driving the RC cir-cuit has been manually constrained to be 6X the minimum,which has found to be a good compromise for a low outputimpedance, resulting in a negligible loading effect, and fornegligible charge injection and leakage during the hold phase.IV. POST-LAYOUT SIMULATION RESULTSThe designed ReDAC circuits occupy a silicon area of910µm2 and 677µm2, respectively (layout of design #1 isshown in Fig.2) and have been characterized under static anddynamic conditions by post-layout simulations including thetransistor-level extracted views and all the parasitics of the RCnetwork and of the digital blocks.The static characterization of the ReDACs reported in Fig.3reveals a maximum (rms) INL of 0.33 LSB (0.1 LSB) anda maximum (rms) DNL of 0.2 LSB (0.01 LSB) for design#1, while for design #2 the maximum (rms) INL is 0.72 LSB(0.34 LSB) and the maximum (rms) DNL is 1.27 LSB (0.07LSB).The energy per conversion for each input code is reported inFig.4. The average energy per conversion is 1.1pJ for design #1and 730fJ for design #2 and in both cases the energy absorbedby the digital blocks (i.e., excluding the energy delivered tothe RC network) accounts for more than 50% of the totalenergy, due to the low capacitance C and to the intrinsicenergy efficiency of the ReDAC.The operation of the ReDACs under dynamic conditions hasbeen simulated for a sine wave input with amplitude of 90%of the input swing and with frequency f0 = 1/(124Tconv),which corresponds to 3.4kHz for design #1 and to 16.8kHzfor design #2. The spectra of the output, sampled in the holdphase of the ReDAC, are reported in Fig.5 and reveal, fordesign #1, an SFDR of 76.8dB, a THD of 66.7dB and a SNDRof 61dB, corresponing to 9.9 effective bits (ENOB). From thesame figure, design #2 achieves an SFDR of 62.4dB, a THD of62.2dB and a SNDR of 58.3dB, corresponding to 9.4 ENOB.Based on Montecarlo simulations performed on 100 sam-ples, it has been found that, keeping T constant, errors dueto process variations in R and C affect the accuracy of theconverter as expected from (6). By the way, it has been verifiedthat the nominal accuracy can be always fully recovered byperforming the calibration procedure described in [10] to re-enforce (4) under process-related variations of τ .The simulated ReDACs performance is summarized inTab.I. As expected, the 40nm ReDACs achieve stronglyimproved performance in terms of sample rate, static anddynamic linearity compared to the FPGA prototype consideredin [10]. Moreover, compared with the capacitive DAC in theSAR ADC in [4], where the DAC energy contribution hasbeen extrapolated based on the ADC energy breakdown for faircomparison, the proposed ReDACs show more than 10X lowerfeature-size normalized area and a 2.3X lower figure of merit(FOM), expressed in energy per conversion per steps. Furtherenergy improvements can be expected by the optimization ofthe logical blocks for low power consumption.V. CONCLUSIONSThe design of two 10-bit ReDACs with 400kS/s and 2MS/ssample rate operating at 600mV power supply in 40nm hasbeen proposed. Based on post-layout simulations, the ReDACsachieve a maximum INL of 0.33/0.72 LSB, a maximum DNLof 0.2/1.27 LSB and a 9.9/9.4 ENOB effective resolutionTABLE IDAC PERFORMANCE COMPARISONUnits [5]c [10]This Thiswork work#1 #2Type C-DAC ReDAC ReDAC ReDACValid. Meas. Meas. Sim. Sim.Techn. nm 180 FPGA 40 40Supply V 0.6 1.8 0.6 0.6Ra kΩ N/A 100 288 128Ca pF 9.2d 2,200 1 0.45Area µm2 163,000 N/A 910 677Norm. Area 106 · F 2 5.03 N/A 0.5 0.3Resolution bit 10 10 10 10Sample Rate kS/S 20 0.3 400 2,000INLmax LSB 0.46c 2.4 0.33 0.72INLrms LSB N/A 0.9 0.10 0.34DNLmax LSB 0.44c 3.3 0.2 1.27DNLrms LSB N/A 0.62 0.01 0.07SNDRb dB 58.3c 43.27 61.0 58.3SFDRb dB 67.7c 51.36 76.8 62.4THDb dB N/A 47.52 66.7 62.2ENOBb bit 9.4c 7.13 9.9 9.4En./conv. pJ 1.7c/1.3 N/A 1.1/0.47 0.73/0.21Tot./AnalogFOM fJ/(c·s) 2.49c N/A 1.1 1.08a for ReDAC only; bbest reported @ 90% swing . sine input.cCDAC performance estimated from the ADC characterization,CDAC energy estimated from ADC energy and power breakdown.dTotal CDAC capacitance.under sine wave input, significantly outperforming the pre-vious ReDAC FPGA-based proof-of-concept prototype. Boththe circuits occupy a silicon area of less than 1, 000µm2 andshow an extremely competitive FOM of 1.1/1.08 fJ/conv.step.,which make them well suited to IoT applications.REFERENCES[1] P. S. Crovetti, F. Musolino, O. Aiello, P. Toledo and R. Rubino,“Breaking the boundaries between analogue and digital,” in Electr. Lett.,vol. 55, no. 12, pp. 672-673, 13 6 2019.[2] O. Aiello, P. Crovetti, L. Lin, M. Alioto, “A pW-Power Hz-RangeOscillator Operating with a 0.3V-1.8V Unregulated Supply,” in IEEEJournal of Solid-State Circuits, Vol.54, no.5, pp.1487-1496, May 2019.[3] M. Saberi, et al. “Analysis of Power Consumption and Linearity inCapacitive Digital-to-Analog Converters Used in Successive Approxi-mation ADCs,” in IEEE Trans. on Circ. and Syst. I: Reg. Papers, vol.58, no. 8, pp. 1736-1748, Aug. 2011.[4] Y. Zhang, E. Bonizzoni and F. Maloberti, “Mismatch and parasiticslimits in capacitors-based SAR ADCs,” 2016 IEEE Int. Conf. on Electr.,Circ. and Syst. (ICECS), Monte Carlo, 2016, pp. 33-36.[5] Z. Zhu and Y. Liang, “A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in0.18-µm CMOS for Medical Implant Devices,” in IEEE Trans. on Circ.and Syst. I: Reg. Papers, vol. 62, no. 9, pp. 2167-2176, Sept. 2015.[6] Westerveld, D. Schinkel, E. van Tuijl, “A 115dB-DR audio DAC with61dBFS out-of-band noise,” ISSCC, San Francisco (CA), 2015.[7] P. S. Crovetti, “All-Digital High Resolution D/A Conversion by DyadicDigital Pulse Modulation,” in IEEE Tran. on Circ. and Syst.I: Reg.Papers, vol. 64, no. 3, pp. 573-584, Mar. 2017.[8] O. Aiello, P. S. Crovetti and M. Alioto, “Fully Synthesizable Low-AreaDigital-to-Analog Converter With Graceful Degradation and DynamicPower-Resolution Scaling,” in IEEE Transactions on Circuits and Sys-tems I: Regular Papers, vol. 66, no. 8, pp. 2865-2875, Aug. 2019.[9] O. Aiello, P. S. Crovetti and M. Alioto, “Standard Cell-Based Ultra-Compact DACs in 40nm” in IEEE Access, vol. 7, pp. 126479 - 126488,Aug. 2019.[10] P. S. Crovetti, R. Rubino and F. Musolino, “Relaxation digital-to-analogue converter,” in Electr. Lett., vol.55, no.12, pp. 685-688, 2019.

https://iris.polito.it/retrieve/handle/11583/2767652/288576/5139.pdf

Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

Abstract

Similar works

Full text

Available Versions

Archivio istituzionale della ricerca - Università di Genova

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)